core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead
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23358b5d29
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@ -38,18 +38,19 @@ class BankMachine(Module):
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self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba))
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# # #
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auto_precharge = Signal()
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# Command buffer
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cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
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cmd_bufferPre = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
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cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
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cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
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self.submodules += cmd_buffer, cmd_bufferPre
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self.submodules += cmd_buffer_lookahead, cmd_buffer
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self.comb += [
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req.connect(cmd_bufferPre.sink, omit=["wdata_valid", "wdata_ready",
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req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready",
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"rdata_valid", "rdata_ready",
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"lock"]),
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cmd_bufferPre.source.connect(cmd_buffer.sink),
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cmd_buffer_lookahead.source.connect(cmd_buffer.sink),
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cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
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req.lock.eq(cmd_buffer.source.valid),
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]
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@ -91,8 +92,8 @@ class BankMachine(Module):
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# Auto Precharge
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self.comb += [
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If(cmd_bufferPre.source.valid & cmd_buffer.source.valid,
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If(slicer.row(cmd_bufferPre.source.adr) != slicer.row(cmd_buffer.source.adr),
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If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid,
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If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr),
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auto_precharge.eq(self.precharge_timer.done & (track_close == 0))
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)
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)
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