Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

init: split by memtype

This commit is contained in:
Florent Kermarrec 2019-09-09 12:10:48 +02:00
parent 0b24b817e3
commit 6e176d40ac
1 changed files with 359 additions and 329 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
litedram/init.py
View File

@ -8,9 +8,6 @@
from migen import log2_int
def get_sdram_phy_init_sequence(phy_settings, timing_settings):
# init sequence
cmds = {
"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
"MODE_REGISTER": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
@ -19,10 +16,9 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
"CKE": "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
}
# SDR ----------------------------------------------------------------------------------------------
def get_sdr_phy_init_sequence(phy_settings, timing_settings):
cl = phy_settings.cl
mr1 = None
if phy_settings.memtype == "SDR":
bl = 1
mr = log2_int(bl) + (cl << 4)
reset_dll = 1 << 8
@ -37,7 +33,11 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]
elif phy_settings.memtype == "DDR":
return init_sequence, None
# DDR ----------------------------------------------------------------------------------------------
def get_ddr_phy_init_sequence(phy_settings, timing_settings):
cl = phy_settings.cl
bl = 4
mr = log2_int(bl) + (cl << 4)
emr = 0
@ -54,7 +54,11 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]
elif phy_settings.memtype == "LPDDR":
return init_sequence, None
# LPDDR --------------------------------------------------------------------------------------------
def get_lpddr_phy_init_sequence(phy_settings, timing_settings):
cl = phy_settings.cl
bl = 4
mr = log2_int(bl) + (cl << 4)
emr = 0
@ -71,7 +75,11 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]
elif phy_settings.memtype == "DDR2":
return init_sequence, mr1
# DDR2 ---------------------------------------------------------------------------------------------
def get_ddr2_phy_init_sequence(phy_settings, timing_settings):
cl = phy_settings.cl
bl = 4
wr = 2
mr = log2_int(bl) + (cl << 4) + (wr << 9)
@ -95,7 +103,12 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
]
elif phy_settings.memtype == "DDR3":
return init_sequence, None
# DDR3 ---------------------------------------------------------------------------------------------
def get_ddr3_phy_init_sequence(phy_settings, timing_settings):
cl = phy_settings.cl
bl = 8
cwl = phy_settings.cwl
@ -194,7 +207,12 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
]
elif phy_settings.memtype == "DDR4":
return init_sequence, mr1
# DDR4 ---------------------------------------------------------------------------------------------
def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
cl = phy_settings.cl
bl = 8
cwl = phy_settings.cwl
@ -343,12 +361,22 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
]
else:
raise NotImplementedError("Unsupported memory type: " + phy_settings.memtype)
return init_sequence, mr1
# Init Sequence ------------------------------------------------------------------------------------
def get_sdram_phy_init_sequence(phy_settings, timing_settings):
return {
"SDR" : get_sdr_phy_init_sequence,
"DDR" : get_ddr_phy_init_sequence,
"LPDDR": get_lpddr_phy_init_sequence,
"DDR2" : get_ddr2_phy_init_sequence,
"DDR3" : get_ddr3_phy_init_sequence,
"DDR4" : get_ddr4_phy_init_sequence,
}[phy_settings.memtype](phy_settings, timing_settings)
# C Header -----------------------------------------------------------------------------------------
def get_sdram_phy_c_header(phy_settings, timing_settings):
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
@ -427,6 +455,8 @@ const unsigned long sdram_dfii_pix_rddata_addr[{n}] = {{
return r
# Python Header ------------------------------------------------------------------------------------
def get_sdram_phy_py_header(phy_settings, timing_settings):
r = ""
r += "dfii_control_sel = 0x01\n"