init: split by memtype
This commit is contained in:
Florent Kermarrec
parent
0b24b817e3
commit
6e176d40ac
688
litedram/init.py
688
litedram/init.py
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@ -8,347 +8,375 @@
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from migen import log2_int
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cmds = {
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"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"UNRESET": "DFII_CONTROL_ODT|DFII_CONTROL_RESET_N",
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"CKE": "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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}
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def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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# init sequence
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cmds = {
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"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"UNRESET": "DFII_CONTROL_ODT|DFII_CONTROL_RESET_N",
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"CKE": "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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}
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# SDR ----------------------------------------------------------------------------------------------
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def get_sdr_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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mr1 = None
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bl = 1
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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if phy_settings.memtype == "SDR":
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bl = 1
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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return init_sequence, None
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elif phy_settings.memtype == "DDR":
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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# DDR ----------------------------------------------------------------------------------------------
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def get_ddr_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif phy_settings.memtype == "LPDDR":
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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return init_sequence, None
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif phy_settings.memtype == "DDR2":
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bl = 4
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wr = 2
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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emr = 0
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emr2 = 0
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emr3 = 0
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reset_dll = 1 << 8
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ocd = 7 << 7
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register 3", emr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register 2", emr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200),
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("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
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]
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elif phy_settings.memtype == "DDR3":
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bl = 8
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cwl = phy_settings.cwl
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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4: 0b10,
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8: 0b00
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}
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cl_to_mr0 = {
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5: 0b0010,
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6: 0b0100,
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7: 0b0110,
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8: 0b1000,
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9: 0b1010,
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10: 0b1100,
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11: 0b1110,
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12: 0b0001,
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13: 0b0011,
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14: 0b0101
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}
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wr_to_mr0 = {
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16: 0b000,
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5: 0b001,
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6: 0b010,
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7: 0b011,
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8: 0b100,
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10: 0b101,
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12: 0b110,
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14: 0b111
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}
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mr0 = bl_to_mr0[bl]
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mr0 |= (cl_to_mr0[cl] & 1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= dll_reset << 8
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mr0 |= wr_to_mr0[wr] << 9
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return mr0
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def format_mr1(ron, rtt_nom):
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mr1 = ((ron >> 0) & 1) << 1
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mr1 |= ((ron >> 1) & 1) << 5
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mr1 |= ((rtt_nom >> 0) & 1) << 2
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mr1 |= ((rtt_nom >> 1) & 1) << 6
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mr1 |= ((rtt_nom >> 2) & 1) << 9
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return mr1
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def format_mr2(cwl, rtt_wr):
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mr2 = (cwl-5) << 3
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mr2 |= rtt_wr << 9
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return mr2
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z_to_rtt_nom = {
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"disabled" : 0,
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"60ohm" : 1,
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"120ohm" : 2,
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"40ohm" : 3,
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"20ohm" : 4,
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"30ohm" : 5
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}
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z_to_rtt_wr = {
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"disabled" : 0,
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"60ohm" : 1,
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"120ohm" : 2,
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}
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z_to_ron = {
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"40ohm" : 0,
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"34ohm" : 1,
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}
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# default electrical settings (point to point)
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rtt_nom = "60ohm"
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rtt_wr = "60ohm"
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ron = "34ohm"
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# override electrical settings if specified
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if hasattr(phy_settings, "rtt_nom"):
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rtt_nom = phy_settings.rtt_nom
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if hasattr(phy_settings, "rtt_wr"):
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rtt_wr = phy_settings.rtt_wr
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if hasattr(phy_settings, "ron"):
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ron = phy_settings.ron
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wr = max(timing_settings.tWTR*phy_settings.nphases, 5) # >= ceiling(tWR/tCK)
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mr0 = format_mr0(bl, cl, wr, 1)
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mr1 = format_mr1(z_to_ron[ron], z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = 0
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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elif phy_settings.memtype == "DDR4":
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bl = 8
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cwl = phy_settings.cwl
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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4: 0b10,
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8: 0b00
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}
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cl_to_mr0 = {
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9: 0b00000,
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10: 0b00001,
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11: 0b00010,
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12: 0b00011,
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13: 0b00100,
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14: 0b00101,
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15: 0b00110,
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16: 0b00111,
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18: 0b01000,
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20: 0b01001,
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22: 0b01010,
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24: 0b01011,
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23: 0b01100,
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17: 0b01101,
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19: 0b01110,
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21: 0b01111,
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25: 0b10000,
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26: 0b10001,
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27: 0b10010,
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28: 0b10011,
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29: 0b10100,
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30: 0b10101,
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31: 0b10110,
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32: 0b10111,
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}
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wr_to_mr0 = {
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10: 0b0000,
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12: 0b0001,
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14: 0b0010,
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16: 0b0011,
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18: 0b0100,
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20: 0b0101,
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24: 0b0110,
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22: 0b0111,
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26: 0b1000,
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28: 0b1001,
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}
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mr0 = bl_to_mr0[bl]
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mr0 |= (cl_to_mr0[cl] & 0b1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= ((cl_to_mr0[cl] >> 4) & 0b1) << 12
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mr0 |= dll_reset << 8
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mr0 |= (wr_to_mr0[wr] & 0b111) << 9
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mr0 |= (wr_to_mr0[wr] >> 3) << 13
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return mr0
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def format_mr1(dll_enable, ron, rtt_nom):
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mr1 = dll_enable
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mr1 |= ((ron >> 0) & 0b1) << 1
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mr1 |= ((ron >> 1) & 0b1) << 2
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mr1 |= ((rtt_nom >> 0) & 0b1) << 8
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mr1 |= ((rtt_nom >> 1) & 0b1) << 9
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mr1 |= ((rtt_nom >> 2) & 0b1) << 10
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return mr1
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def format_mr2(cwl, rtt_wr):
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cwl_to_mr2 = {
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9: 0b000,
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10: 0b001,
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11: 0b010,
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12: 0b011,
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14: 0b100,
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16: 0b101,
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18: 0b110,
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20: 0b111
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}
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mr2 = cwl_to_mr2[cwl] << 3
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mr2 |= rtt_wr << 9
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return mr2
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def format_mr6(tccd):
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tccd_to_mr6 = {
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4: 0b000,
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5: 0b001,
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6: 0b010,
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7: 0b011,
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8: 0b100
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}
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mr6 = tccd_to_mr6[tccd] << 10
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return mr6
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z_to_rtt_nom = {
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"disabled" : 0b000,
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"60ohm" : 0b001,
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"120ohm" : 0b010,
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"40ohm" : 0b011,
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"240ohm" : 0b100,
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"48ohm" : 0b101,
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"80ohm" : 0b110,
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"34ohm" : 0b111
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}
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z_to_rtt_wr = {
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"disabled" : 0b000,
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"120ohm" : 0b001,
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"240ohm" : 0b010,
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"high-z" : 0b011,
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"80ohm" : 0b100,
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}
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z_to_ron = {
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"34ohm" : 0b00,
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"48ohm" : 0b01,
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}
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# default electrical settings (point to point)
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rtt_nom = "40ohm"
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rtt_wr = "120ohm"
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ron = "34ohm"
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# override electrical settings if specified
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if hasattr(phy_settings, "rtt_nom"):
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rtt_nom = phy_settings.rtt_nom
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if hasattr(phy_settings, "rtt_wr"):
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rtt_wr = phy_settings.rtt_wr
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if hasattr(phy_settings, "ron"):
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ron = phy_settings.ron
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wr = max(timing_settings.tWTR*phy_settings.nphases, 10) # >= ceiling(tWR/tCK)
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mr0 = format_mr0(bl, cl, wr, 1)
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mr1 = format_mr1(1, z_to_ron[ron], z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = 0
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mr4 = 0
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mr5 = 0
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mr6 = format_mr6(4) # FIXME: tCCD
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 6", mr6, 6, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 5", mr5, 5, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 4", mr4, 4, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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else:
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raise NotImplementedError("Unsupported memory type: " + phy_settings.memtype)
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# LPDDR --------------------------------------------------------------------------------------------
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def get_lpddr_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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||||
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
|
||||
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
|
||||
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
|
||||
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
|
||||
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
|
||||
]
|
||||
|
||||
return init_sequence, mr1
|
||||
|
||||
# DDR2 ---------------------------------------------------------------------------------------------
|
||||
def get_ddr2_phy_init_sequence(phy_settings, timing_settings):
|
||||
cl = phy_settings.cl
|
||||
bl = 4
|
||||
wr = 2
|
||||
mr = log2_int(bl) + (cl << 4) + (wr << 9)
|
||||
emr = 0
|
||||
emr2 = 0
|
||||
emr3 = 0
|
||||
reset_dll = 1 << 8
|
||||
ocd = 7 << 7
|
||||
|
||||
init_sequence = [
|
||||
("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
|
||||
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
|
||||
("Load Extended Mode Register 3", emr3, 3, cmds["MODE_REGISTER"], 0),
|
||||
("Load Extended Mode Register 2", emr2, 2, cmds["MODE_REGISTER"], 0),
|
||||
("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
|
||||
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
|
||||
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
|
||||
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
|
||||
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200),
|
||||
("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
|
||||
("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
|
||||
]
|
||||
|
||||
return init_sequence, None
|
||||
|
||||
# DDR3 ---------------------------------------------------------------------------------------------
|
||||
def get_ddr3_phy_init_sequence(phy_settings, timing_settings):
|
||||
cl = phy_settings.cl
|
||||
bl = 8
|
||||
cwl = phy_settings.cwl
|
||||
|
||||
def format_mr0(bl, cl, wr, dll_reset):
|
||||
bl_to_mr0 = {
|
||||
4: 0b10,
|
||||
8: 0b00
|
||||
}
|
||||
cl_to_mr0 = {
|
||||
5: 0b0010,
|
||||
6: 0b0100,
|
||||
7: 0b0110,
|
||||
8: 0b1000,
|
||||
9: 0b1010,
|
||||
10: 0b1100,
|
||||
11: 0b1110,
|
||||
12: 0b0001,
|
||||
13: 0b0011,
|
||||
14: 0b0101
|
||||
}
|
||||
wr_to_mr0 = {
|
||||
16: 0b000,
|
||||
5: 0b001,
|
||||
6: 0b010,
|
||||
7: 0b011,
|
||||
8: 0b100,
|
||||
10: 0b101,
|
||||
12: 0b110,
|
||||
14: 0b111
|
||||
}
|
||||
mr0 = bl_to_mr0[bl]
|
||||
mr0 |= (cl_to_mr0[cl] & 1) << 2
|
||||
mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
|
||||
mr0 |= dll_reset << 8
|
||||
mr0 |= wr_to_mr0[wr] << 9
|
||||
return mr0
|
||||
|
||||
def format_mr1(ron, rtt_nom):
|
||||
mr1 = ((ron >> 0) & 1) << 1
|
||||
mr1 |= ((ron >> 1) & 1) << 5
|
||||
mr1 |= ((rtt_nom >> 0) & 1) << 2
|
||||
mr1 |= ((rtt_nom >> 1) & 1) << 6
|
||||
mr1 |= ((rtt_nom >> 2) & 1) << 9
|
||||
return mr1
|
||||
|
||||
def format_mr2(cwl, rtt_wr):
|
||||
mr2 = (cwl-5) << 3
|
||||
mr2 |= rtt_wr << 9
|
||||
return mr2
|
||||
|
||||
z_to_rtt_nom = {
|
||||
"disabled" : 0,
|
||||
"60ohm" : 1,
|
||||
"120ohm" : 2,
|
||||
"40ohm" : 3,
|
||||
"20ohm" : 4,
|
||||
"30ohm" : 5
|
||||
}
|
||||
|
||||
z_to_rtt_wr = {
|
||||
"disabled" : 0,
|
||||
"60ohm" : 1,
|
||||
"120ohm" : 2,
|
||||
}
|
||||
|
||||
z_to_ron = {
|
||||
"40ohm" : 0,
|
||||
"34ohm" : 1,
|
||||
}
|
||||
|
||||
# default electrical settings (point to point)
|
||||
rtt_nom = "60ohm"
|
||||
rtt_wr = "60ohm"
|
||||
ron = "34ohm"
|
||||
|
||||
# override electrical settings if specified
|
||||
if hasattr(phy_settings, "rtt_nom"):
|
||||
rtt_nom = phy_settings.rtt_nom
|
||||
if hasattr(phy_settings, "rtt_wr"):
|
||||
rtt_wr = phy_settings.rtt_wr
|
||||
if hasattr(phy_settings, "ron"):
|
||||
ron = phy_settings.ron
|
||||
|
||||
wr = max(timing_settings.tWTR*phy_settings.nphases, 5) # >= ceiling(tWR/tCK)
|
||||
mr0 = format_mr0(bl, cl, wr, 1)
|
||||
mr1 = format_mr1(z_to_ron[ron], z_to_rtt_nom[rtt_nom])
|
||||
mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
|
||||
mr3 = 0
|
||||
|
||||
init_sequence = [
|
||||
("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
|
||||
("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
|
||||
("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
|
||||
("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
|
||||
]
|
||||
|
||||
return init_sequence, mr1
|
||||
|
||||
# DDR4 ---------------------------------------------------------------------------------------------
|
||||
def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
|
||||
cl = phy_settings.cl
|
||||
bl = 8
|
||||
cwl = phy_settings.cwl
|
||||
|
||||
def format_mr0(bl, cl, wr, dll_reset):
|
||||
bl_to_mr0 = {
|
||||
4: 0b10,
|
||||
8: 0b00
|
||||
}
|
||||
cl_to_mr0 = {
|
||||
9: 0b00000,
|
||||
10: 0b00001,
|
||||
11: 0b00010,
|
||||
12: 0b00011,
|
||||
13: 0b00100,
|
||||
14: 0b00101,
|
||||
15: 0b00110,
|
||||
16: 0b00111,
|
||||
18: 0b01000,
|
||||
20: 0b01001,
|
||||
22: 0b01010,
|
||||
24: 0b01011,
|
||||
23: 0b01100,
|
||||
17: 0b01101,
|
||||
19: 0b01110,
|
||||
21: 0b01111,
|
||||
25: 0b10000,
|
||||
26: 0b10001,
|
||||
27: 0b10010,
|
||||
28: 0b10011,
|
||||
29: 0b10100,
|
||||
30: 0b10101,
|
||||
31: 0b10110,
|
||||
32: 0b10111,
|
||||
}
|
||||
wr_to_mr0 = {
|
||||
10: 0b0000,
|
||||
12: 0b0001,
|
||||
14: 0b0010,
|
||||
16: 0b0011,
|
||||
18: 0b0100,
|
||||
20: 0b0101,
|
||||
24: 0b0110,
|
||||
22: 0b0111,
|
||||
26: 0b1000,
|
||||
28: 0b1001,
|
||||
}
|
||||
mr0 = bl_to_mr0[bl]
|
||||
mr0 |= (cl_to_mr0[cl] & 0b1) << 2
|
||||
mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
|
||||
mr0 |= ((cl_to_mr0[cl] >> 4) & 0b1) << 12
|
||||
mr0 |= dll_reset << 8
|
||||
mr0 |= (wr_to_mr0[wr] & 0b111) << 9
|
||||
mr0 |= (wr_to_mr0[wr] >> 3) << 13
|
||||
return mr0
|
||||
|
||||
def format_mr1(dll_enable, ron, rtt_nom):
|
||||
mr1 = dll_enable
|
||||
mr1 |= ((ron >> 0) & 0b1) << 1
|
||||
mr1 |= ((ron >> 1) & 0b1) << 2
|
||||
mr1 |= ((rtt_nom >> 0) & 0b1) << 8
|
||||
mr1 |= ((rtt_nom >> 1) & 0b1) << 9
|
||||
mr1 |= ((rtt_nom >> 2) & 0b1) << 10
|
||||
return mr1
|
||||
|
||||
def format_mr2(cwl, rtt_wr):
|
||||
cwl_to_mr2 = {
|
||||
9: 0b000,
|
||||
10: 0b001,
|
||||
11: 0b010,
|
||||
12: 0b011,
|
||||
14: 0b100,
|
||||
16: 0b101,
|
||||
18: 0b110,
|
||||
20: 0b111
|
||||
}
|
||||
mr2 = cwl_to_mr2[cwl] << 3
|
||||
mr2 |= rtt_wr << 9
|
||||
return mr2
|
||||
|
||||
def format_mr6(tccd):
|
||||
tccd_to_mr6 = {
|
||||
4: 0b000,
|
||||
5: 0b001,
|
||||
6: 0b010,
|
||||
7: 0b011,
|
||||
8: 0b100
|
||||
}
|
||||
mr6 = tccd_to_mr6[tccd] << 10
|
||||
return mr6
|
||||
|
||||
z_to_rtt_nom = {
|
||||
"disabled" : 0b000,
|
||||
"60ohm" : 0b001,
|
||||
"120ohm" : 0b010,
|
||||
"40ohm" : 0b011,
|
||||
"240ohm" : 0b100,
|
||||
"48ohm" : 0b101,
|
||||
"80ohm" : 0b110,
|
||||
"34ohm" : 0b111
|
||||
}
|
||||
|
||||
z_to_rtt_wr = {
|
||||
"disabled" : 0b000,
|
||||
"120ohm" : 0b001,
|
||||
"240ohm" : 0b010,
|
||||
"high-z" : 0b011,
|
||||
"80ohm" : 0b100,
|
||||
}
|
||||
|
||||
z_to_ron = {
|
||||
"34ohm" : 0b00,
|
||||
"48ohm" : 0b01,
|
||||
}
|
||||
|
||||
# default electrical settings (point to point)
|
||||
rtt_nom = "40ohm"
|
||||
rtt_wr = "120ohm"
|
||||
ron = "34ohm"
|
||||
|
||||
# override electrical settings if specified
|
||||
if hasattr(phy_settings, "rtt_nom"):
|
||||
rtt_nom = phy_settings.rtt_nom
|
||||
if hasattr(phy_settings, "rtt_wr"):
|
||||
rtt_wr = phy_settings.rtt_wr
|
||||
if hasattr(phy_settings, "ron"):
|
||||
ron = phy_settings.ron
|
||||
|
||||
wr = max(timing_settings.tWTR*phy_settings.nphases, 10) # >= ceiling(tWR/tCK)
|
||||
mr0 = format_mr0(bl, cl, wr, 1)
|
||||
mr1 = format_mr1(1, z_to_ron[ron], z_to_rtt_nom[rtt_nom])
|
||||
mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
|
||||
mr3 = 0
|
||||
mr4 = 0
|
||||
mr5 = 0
|
||||
mr6 = format_mr6(4) # FIXME: tCCD
|
||||
|
||||
init_sequence = [
|
||||
("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
|
||||
("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
|
||||
("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 6", mr6, 6, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 5", mr5, 5, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 4", mr4, 4, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
|
||||
("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
|
||||
("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
|
||||
]
|
||||
|
||||
return init_sequence, mr1
|
||||
|
||||
# Init Sequence ------------------------------------------------------------------------------------
|
||||
|
||||
def get_sdram_phy_init_sequence(phy_settings, timing_settings):
|
||||
return {
|
||||
"SDR" : get_sdr_phy_init_sequence,
|
||||
"DDR" : get_ddr_phy_init_sequence,
|
||||
"LPDDR": get_lpddr_phy_init_sequence,
|
||||
"DDR2" : get_ddr2_phy_init_sequence,
|
||||
"DDR3" : get_ddr3_phy_init_sequence,
|
||||
"DDR4" : get_ddr4_phy_init_sequence,
|
||||
}[phy_settings.memtype](phy_settings, timing_settings)
|
||||
|
||||
# C Header -----------------------------------------------------------------------------------------
|
||||
|
||||
def get_sdram_phy_c_header(phy_settings, timing_settings):
|
||||
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
|
||||
|
|
@ -427,6 +455,8 @@ const unsigned long sdram_dfii_pix_rddata_addr[{n}] = {{
|
|||
|
||||
return r
|
||||
|
||||
# Python Header ------------------------------------------------------------------------------------
|
||||
|
||||
def get_sdram_phy_py_header(phy_settings, timing_settings):
|
||||
r = ""
|
||||
r += "dfii_control_sel = 0x01\n"
|
||||
|
|
|
|||
Loading…
Reference in New Issue