phy: add Artix7 a7ddrphy (Arty, Nexys Video)
This commit is contained in:
Florent Kermarrec
parent
d48c298363
commit
6ef6e2f388
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# tCK=2.5ns CL=7 CWL=6
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from litex.gen import *
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from litex.soc.interconnect.csr import *
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from litedram.phy.dfi import *
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from litedram import settings as sdram_settings
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class A7DDRPHY(Module, AutoCSR):
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def __init__(self, pads):
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addressbits = len(pads.a)
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bankbits = len(pads.ba)
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databits = len(pads.dq)
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nphases = 4
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self._wlevel_en = CSRStorage()
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self._wlevel_strobe = CSR()
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self._dly_sel = CSRStorage(databits//8)
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self._rdly_dq_rst = CSR()
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self._rdly_dq_inc = CSR()
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self._rdly_dq_bitslip = CSR()
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self.settings = sdram_settings.PhySettings(
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memtype="DDR3",
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dfi_databits=2*databits,
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nphases=nphases,
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rdphase=0,
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wrphase=2,
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rdcmdphase=1,
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wrcmdphase=0,
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cl=7,
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cwl=6,
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read_latency=6,
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write_latency=2
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)
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self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
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# # #
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# Clock
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sd_clk_se = Signal()
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self.specials += [
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=sd_clk_se,
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i_OCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D1=0, i_D2=1, i_D3=0, i_D4=1,
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i_D5=0, i_D6=1, i_D7=0, i_D8=1
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),
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Instance("OBUFDS",
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i_I=sd_clk_se,
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o_O=pads.clk_p,
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o_OB=pads.clk_n
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)
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]
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# Addresses and commands
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for i in range(addressbits):
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self.specials += \
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=pads.a[i],
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i_OCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D1=self.dfi.phases[0].address[i], i_D2=self.dfi.phases[0].address[i],
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i_D3=self.dfi.phases[1].address[i], i_D4=self.dfi.phases[1].address[i],
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i_D5=self.dfi.phases[2].address[i], i_D6=self.dfi.phases[2].address[i],
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i_D7=self.dfi.phases[3].address[i], i_D8=self.dfi.phases[3].address[i]
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)
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for i in range(bankbits):
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self.specials += \
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=pads.ba[i],
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i_OCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D1=self.dfi.phases[0].bank[i], i_D2=self.dfi.phases[0].bank[i],
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i_D3=self.dfi.phases[1].bank[i], i_D4=self.dfi.phases[1].bank[i],
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i_D5=self.dfi.phases[2].bank[i], i_D6=self.dfi.phases[2].bank[i],
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i_D7=self.dfi.phases[3].bank[i], i_D8=self.dfi.phases[3].bank[i]
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)
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controls = ["ras_n", "cas_n", "we_n", "cke", "odt", "reset_n"]
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if hasattr(pads, "cs_n"):
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controls.append("cs_n")
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for name in controls:
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self.specials += \
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=getattr(pads, name),
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i_OCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D1=getattr(self.dfi.phases[0], name), i_D2=getattr(self.dfi.phases[0], name),
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i_D3=getattr(self.dfi.phases[1], name), i_D4=getattr(self.dfi.phases[1], name),
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i_D5=getattr(self.dfi.phases[2], name), i_D6=getattr(self.dfi.phases[2], name),
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i_D7=getattr(self.dfi.phases[3], name), i_D8=getattr(self.dfi.phases[3], name)
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)
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# DQS and DM
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oe_dqs = Signal()
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dqs_serdes_pattern = Signal(8)
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self.comb += \
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If(self._wlevel_en.storage,
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If(self._wlevel_strobe.re,
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dqs_serdes_pattern.eq(0b00000001)
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).Else(
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dqs_serdes_pattern.eq(0b00000000)
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)
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).Else(
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dqs_serdes_pattern.eq(0b01010101)
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)
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for i in range(databits//8):
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self.specials += \
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=pads.dm[i],
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i_OCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D1=self.dfi.phases[0].wrdata_mask[i], i_D2=self.dfi.phases[0].wrdata_mask[databits//8+i],
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i_D3=self.dfi.phases[1].wrdata_mask[i], i_D4=self.dfi.phases[1].wrdata_mask[databits//8+i],
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i_D5=self.dfi.phases[2].wrdata_mask[i], i_D6=self.dfi.phases[2].wrdata_mask[databits//8+i],
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i_D7=self.dfi.phases[3].wrdata_mask[i], i_D8=self.dfi.phases[3].wrdata_mask[databits//8+i]
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)
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dqs = Signal()
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dqs_t = Signal()
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self.specials += [
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=dqs, o_TQ=dqs_t,
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i_OCE=1, i_TCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x_dqs"), i_CLKDIV=ClockSignal(),
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i_D1=dqs_serdes_pattern[0], i_D2=dqs_serdes_pattern[1],
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i_D3=dqs_serdes_pattern[2], i_D4=dqs_serdes_pattern[3],
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i_D5=dqs_serdes_pattern[4], i_D6=dqs_serdes_pattern[5],
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i_D7=dqs_serdes_pattern[6], i_D8=dqs_serdes_pattern[7],
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i_T1=~oe_dqs
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),
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Instance("OBUFTDS",
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i_I=dqs, i_T=dqs_t,
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o_O=pads.dqs_p[i], o_OB=pads.dqs_n[i]
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)
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]
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# DQ
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oe_dq = Signal()
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for i in range(databits):
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dq_o = Signal()
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dq_i_nodelay = Signal()
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dq_i_delayed = Signal()
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dq_t = Signal()
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self.specials += [
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=dq_o, o_TQ=dq_t,
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i_OCE=1, i_TCE=1,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D1=self.dfi.phases[0].wrdata[i], i_D2=self.dfi.phases[0].wrdata[databits+i],
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i_D3=self.dfi.phases[1].wrdata[i], i_D4=self.dfi.phases[1].wrdata[databits+i],
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i_D5=self.dfi.phases[2].wrdata[i], i_D6=self.dfi.phases[2].wrdata[databits+i],
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i_D7=self.dfi.phases[3].wrdata[i], i_D8=self.dfi.phases[3].wrdata[databits+i],
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i_T1=~oe_dq
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),
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Instance("ISERDESE2",
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p_DATA_WIDTH=8, p_DATA_RATE="DDR",
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p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1, p_IOBDELAY="IFD",
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i_DDLY=dq_i_delayed,
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i_CE1=1,
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i_RST=ResetSignal() | (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re),
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i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_BITSLIP=self._dly_sel.storage[i//8] & self._rdly_dq_bitslip.re,
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o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[databits+i],
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o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[databits+i],
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o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[databits+i],
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o_Q2=self.dfi.phases[3].rddata[i], o_Q1=self.dfi.phases[3].rddata[databits+i]
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),
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Instance("IDELAYE2",
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p_DELAY_SRC="IDATAIN", p_SIGNAL_PATTERN="DATA",
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p_CINVCTRL_SEL="FALSE", p_HIGH_PERFORMANCE_MODE="TRUE", p_REFCLK_FREQUENCY=200.0,
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p_PIPE_SEL="FALSE", p_IDELAY_TYPE="VARIABLE", p_IDELAY_VALUE=6,
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i_C=ClockSignal(),
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i_LD=self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
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i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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i_LDPIPEEN=0, i_INC=1,
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i_IDATAIN=dq_i_nodelay, o_DATAOUT=dq_i_delayed
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),
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Instance("IOBUF",
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i_I=dq_o, o_O=dq_i_nodelay, i_T=dq_t,
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io_IO=pads.dq[i]
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)
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]
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# Flow control
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#
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# total read latency = 6:
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# 2 cycles through OSERDESE2
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# 2 cycles CAS
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# 2 cycles through ISERDESE2
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rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
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for i in range(5):
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n_rddata_en = Signal()
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self.sync += n_rddata_en.eq(rddata_en)
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rddata_en = n_rddata_en
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self.sync += [phase.rddata_valid.eq(rddata_en | self._wlevel_en.storage)
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for phase in self.dfi.phases]
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oe = Signal()
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last_wrdata_en = Signal(4)
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wrphase = self.dfi.phases[self.settings.wrphase]
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self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:3]))
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self.comb += oe.eq(last_wrdata_en[1] | last_wrdata_en[2] | last_wrdata_en[3])
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self.sync += \
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If(self._wlevel_en.storage,
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oe_dqs.eq(1), oe_dq.eq(0)
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).Else(
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oe_dqs.eq(oe), oe_dq.eq(oe)
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)
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