litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC.

For some use cases, we will want to have the CPU + wb_ctrl interface.

litedram/gen.py

@@ -304,7 +304,6 @@ class LiteDRAMCore(SoCCore):
         cpu_type      = core_config["cpu"]
         cpu_variant   = core_config.get("cpu_variant", "standard")
         csr_alignment = core_config.get("csr_alignment", 32)
-        csr_base      = core_config.get("csr_base", None)
         if cpu_type is None:
             kwargs["integrated_rom_size"]  = 0
             kwargs["integrated_sram_size"] = 0
@@ -316,7 +315,6 @@ class LiteDRAMCore(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq,
             cpu_type      = cpu_type,
             cpu_variant   = cpu_variant,
-            csr_base      = csr_base,
             csr_alignment = csr_alignment,
             **kwargs)
 
@@ -378,7 +376,7 @@ class LiteDRAMCore(SoCCore):
         self.comb += platform.request("init_error").eq(self.ddrctrl.init_error.storage)
         # If no CPU, expose a bus control interface to user.
         if cpu_type is None:
-            wb_bus = wishbone.Interface(adr_width=self.csr.address_width)
+            wb_bus = wishbone.Interface(self.bus.address_width)
             self.bus.add_master(master=wb_bus)
             platform.add_extension(wb_bus.get_ios("wb_ctrl"))
             wb_pads = platform.request("wb_ctrl")