phy/lpddr4: make simphy serialization cleaner and easier to read
This commit is contained in:
Jędrzej Boczar
parent
47e8a59511
commit
721b6f874b
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@ -6,7 +6,7 @@
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from migen import *
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from litedram.phy.utils import delayed, Serializer, Deserializer, Latency, SimPad, SimulationPads
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from litedram.phy.utils import delayed, Serializer, Deserializer, Latency, SimPad, SimulationPads, SimSerDesMixin
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from litedram.phy.lpddr4.basephy import LPDDR4PHY, DoubleRateLPDDR4PHY
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@ -25,84 +25,11 @@ class LPDDR4SimulationPads(SimulationPads):
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]
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class _LPDDR4SimPHYMixin:
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"""Common serialization logic for simulation PHYs
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class LPDDR4SimPHY(SimSerDesMixin, LPDDR4PHY):
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"""LPDDR4 simulation PHY with direct 16:1 serializers
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This mixin provides `do_serialization` method for constructing the boilerplate
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serialization/deserialization paths for a simulation PHY. This can serve as a
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reference for implemeing PHYs for concrete FPGAs.
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To make the (de-)serialization work in simulation two additional clock domains
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are required: `sys8x_ddr` and `sys8x_90_ddr`. These correspond to `sys8x` and
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`sys8x_90`, are phase aligned with them and at twice their frequency. These
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clock domains are requried to implement DDR (de-)serialization at 8x sys clock.
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For simulation purpose two additional "DDR" clock domains are requires.
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"""
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def _add_name(self, prefix, kwargs):
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name = prefix + "_" + kwargs.pop("name", "")
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kwargs["name"] = name.strip("_")
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def _serialize(self, **kwargs):
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self._add_name("ser", kwargs)
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ser = Serializer(o_dw=1, **kwargs)
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self.submodules += ser
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def _deserialize(self, **kwargs):
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self._add_name("des", kwargs)
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des = Deserializer(i_dw=1, **kwargs)
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self.submodules += des
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def do_serialization(self, clkdiv, delay, aligned_reset_zero):
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def add_reset_cnt(phase, kwargs):
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if aligned_reset_zero and phase == 0:
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kwargs["reset_cnt"] = 0
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def ser_sdr(phase=0, **kwargs):
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add_reset_cnt(phase, kwargs)
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clk = {0: "sys8x", 90: "sys8x_90"}[phase]
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self._serialize(clk=clk, clkdiv=clkdiv, i_dw=len(kwargs["i"]), **kwargs)
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def ser_ddr(phase=0, **kwargs):
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add_reset_cnt(phase, kwargs)
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# for simulation we require sys8x_ddr clock (=sys16x)
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clk = {0: "sys8x_ddr", 90: "sys8x_90_ddr"}[phase]
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self._serialize(clk=clk, clkdiv=clkdiv, i_dw=len(kwargs["i"]), **kwargs)
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def des_ddr(phase=0, **kwargs):
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add_reset_cnt(phase, kwargs)
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clk = {0: "sys8x_ddr", 90: "sys8x_90_ddr"}[phase]
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self._deserialize(clk=clk, clkdiv=clkdiv, o_dw=len(kwargs["o"]), **kwargs)
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# Clock is shifted 180 degrees to get rising edge in the middle of SDR signals.
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# To achieve that we send negated clock on clk (clk_p).
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ser_ddr(i=~self.out.clk, o=self.pads.clk, name='clk')
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ser_sdr(i=self.out.cke, o=self.pads.cke, name='cke')
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ser_sdr(i=self.out.odt, o=self.pads.odt, name='odt')
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ser_sdr(i=self.out.reset_n, o=self.pads.reset_n, name='reset_n')
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# Command/address
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ser_sdr(i=self.out.cs, o=self.pads.cs, name='cs')
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for i in range(6):
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ser_sdr(i=self.out.ca[i], o=self.pads.ca[i], name=f'ca{i}')
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# Tristate I/O (separate for simulation)
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for i in range(self.databits//8):
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ser_ddr(i=self.out.dmi_o[i], o=self.pads.dmi_o[i], name=f'dmi_o{i}')
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des_ddr(o=self.out.dmi_i[i], i=self.pads.dmi[i], name=f'dmi_i{i}')
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ser_ddr(i=self.out.dqs_o[i], o=self.pads.dqs_o[i], name=f'dqs_o{i}', phase=90)
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des_ddr(o=self.out.dqs_i[i], i=self.pads.dqs[i], name=f'dqs_i{i}', phase=90)
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for i in range(self.databits):
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ser_ddr(i=self.out.dq_o[i], o=self.pads.dq_o[i], name=f'dq_o{i}')
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des_ddr(o=self.out.dq_i[i], i=self.pads.dq[i], name=f'dq_i{i}')
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# Output enable signals
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self.comb += self.pads.dmi_oe.eq(delay(self.out.dmi_oe, cycles=Serializer.LATENCY))
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self.comb += self.pads.dqs_oe.eq(delay(self.out.dqs_oe, cycles=Serializer.LATENCY))
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self.comb += self.pads.dq_oe.eq(delay(self.out.dq_oe, cycles=Serializer.LATENCY))
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class LPDDR4SimPHY(_LPDDR4SimPHYMixin, LPDDR4PHY):
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"""LPDDR4 simulation PHY with direct 16:1 serializers"""
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def __init__(self, aligned_reset_zero=False, **kwargs):
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pads = LPDDR4SimulationPads()
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self.submodules += pads
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@ -112,18 +39,54 @@ class LPDDR4SimPHY(_LPDDR4SimPHYMixin, LPDDR4PHY):
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phytype = "LPDDR4SimPHY",
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**kwargs)
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self.do_serialization(
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clkdiv = "sys",
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delay = lambda sig, cycles: delayed(self, sig, cycles=cycles),
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aligned_reset_zero = aligned_reset_zero,
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)
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delay = lambda sig, cycles: delayed(self, sig, cycles=cycles)
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sdr = dict(clkdiv="sys", clk="sys8x")
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sdr_90 = dict(clkdiv="sys", clk="sys8x_90")
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ddr = dict(clkdiv="sys", clk="sys8x_ddr")
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ddr_90 = dict(clkdiv="sys", clk="sys8x_90_ddr")
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if aligned_reset_zero:
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sdr["reset_cnt"] = 0
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ddr["reset_cnt"] = 0
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# Clock is shifted 180 degrees to get rising edge in the middle of SDR signals.
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# To achieve that we send negated clock on clk (clk_p).
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self.ser(i=~self.out.clk, o=self.pads.clk, name='clk', **ddr)
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self.ser(i=self.out.cke, o=self.pads.cke, name='cke', **sdr)
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self.ser(i=self.out.odt, o=self.pads.odt, name='odt', **sdr)
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self.ser(i=self.out.reset_n, o=self.pads.reset_n, name='reset_n', **sdr)
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# Command/address
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self.ser(i=self.out.cs, o=self.pads.cs, name='cs', **sdr)
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for i in range(6):
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self.ser(i=self.out.ca[i], o=self.pads.ca[i], name=f'ca{i}', **sdr)
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# Tristate I/O (separate for simulation)
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for i in range(self.databits//8):
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self.ser(i=self.out.dmi_o[i], o=self.pads.dmi_o[i], name=f'dmi_o{i}', **ddr)
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self.des(o=self.out.dmi_i[i], i=self.pads.dmi[i], name=f'dmi_i{i}', **ddr)
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self.ser(i=self.out.dqs_o[i], o=self.pads.dqs_o[i], name=f'dqs_o{i}', **ddr_90)
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self.des(o=self.out.dqs_i[i], i=self.pads.dqs[i], name=f'dqs_i{i}', **ddr_90)
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for i in range(self.databits):
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self.ser(i=self.out.dq_o[i], o=self.pads.dq_o[i], name=f'dq_o{i}', **ddr)
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self.des(o=self.out.dq_i[i], i=self.pads.dq[i], name=f'dq_i{i}', **ddr)
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# Output enable signals
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self.comb += [
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self.pads.dmi_oe.eq(delay(self.out.dmi_oe, cycles=Serializer.LATENCY)),
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self.pads.dqs_oe.eq(delay(self.out.dqs_oe, cycles=Serializer.LATENCY)),
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self.pads.dq_oe.eq(delay(self.out.dq_oe, cycles=Serializer.LATENCY)),
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]
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class DoubleRateLPDDR4SimPHY(_LPDDR4SimPHYMixin, DoubleRateLPDDR4PHY):
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class DoubleRateLPDDR4SimPHY(SimSerDesMixin, DoubleRateLPDDR4PHY):
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"""LPDDR4 simulation PHY basing of DoubleRateLPDDR4PHY
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`DoubleRateLPDDR4PHY` performs a single serialization step between `sys` and `sys2x`,
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so this PHY wrapper has to do the serialization between `sys2x` and `sys8x` (SDR/DDR).
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For simulation purpose two additional "DDR" clock domains are requires.
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"""
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def __init__(self, aligned_reset_zero=False, **kwargs):
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pads = LPDDR4SimulationPads()
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@ -135,9 +98,43 @@ class DoubleRateLPDDR4SimPHY(_LPDDR4SimPHYMixin, DoubleRateLPDDR4PHY):
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**kwargs)
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self.submodules.half_delay = ClockDomainsRenamer("sys2x")(Module())
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delay = lambda sig, cycles: delayed(self.half_delay, sig, cycles=cycles)
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self.do_serialization(
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clkdiv = "sys2x",
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delay = lambda sig, cycles: delayed(self.half_delay, sig, cycles=cycles),
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aligned_reset_zero = aligned_reset_zero,
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)
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sdr = dict(clkdiv="sys2x", clk="sys8x")
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sdr_90 = dict(clkdiv="sys2x", clk="sys8x_90")
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ddr = dict(clkdiv="sys2x", clk="sys8x_ddr")
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ddr_90 = dict(clkdiv="sys2x", clk="sys8x_90_ddr")
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if aligned_reset_zero:
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sdr["reset_cnt"] = 0
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ddr["reset_cnt"] = 0
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# Clock is shifted 180 degrees to get rising edge in the middle of SDR signals.
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# To achieve that we send negated clock on clk (clk_p).
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self.ser(i=~self.out.clk, o=self.pads.clk, name='clk', **ddr)
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self.ser(i=self.out.cke, o=self.pads.cke, name='cke', **sdr)
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self.ser(i=self.out.odt, o=self.pads.odt, name='odt', **sdr)
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self.ser(i=self.out.reset_n, o=self.pads.reset_n, name='reset_n', **sdr)
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# Command/address
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self.ser(i=self.out.cs, o=self.pads.cs, name='cs', **sdr)
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for i in range(6):
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self.ser(i=self.out.ca[i], o=self.pads.ca[i], name=f'ca{i}', **sdr)
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# Tristate I/O (separate for simulation)
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for i in range(self.databits//8):
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self.ser(i=self.out.dmi_o[i], o=self.pads.dmi_o[i], name=f'dmi_o{i}', **ddr)
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self.des(o=self.out.dmi_i[i], i=self.pads.dmi[i], name=f'dmi_i{i}', **ddr)
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self.ser(i=self.out.dqs_o[i], o=self.pads.dqs_o[i], name=f'dqs_o{i}', **ddr_90)
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self.des(o=self.out.dqs_i[i], i=self.pads.dqs[i], name=f'dqs_i{i}', **ddr_90)
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for i in range(self.databits):
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self.ser(i=self.out.dq_o[i], o=self.pads.dq_o[i], name=f'dq_o{i}', **ddr)
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self.des(o=self.out.dq_i[i], i=self.pads.dq[i], name=f'dq_i{i}', **ddr)
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# Output enable signals
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self.comb += [
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self.pads.dmi_oe.eq(delay(self.out.dmi_oe, cycles=Serializer.LATENCY)),
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self.pads.dqs_oe.eq(delay(self.out.dqs_oe, cycles=Serializer.LATENCY)),
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self.pads.dq_oe.eq(delay(self.out.dq_oe, cycles=Serializer.LATENCY)),
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]
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@ -320,6 +320,21 @@ class Deserializer(Module):
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sd_clkdiv += self.o.eq(Cat(as_array(o_pre_d)[:-1], as_array(o_pre)[-1]))
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class SimSerDesMixin:
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"""Helper class for easier (de-)serialization to simulation pads."""
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def ser(self, *, i, o, clkdiv, clk, name="", **kwargs):
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assert len(o) == 1
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kwargs = dict(i=i, i_dw=len(i), o=o, o_dw=1, clk=clk, clkdiv=clkdiv,
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name=f"ser_{name}".strip("_"), **kwargs)
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self.submodules += Serializer(**kwargs)
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def des(self, *, i, o, clkdiv, clk, name="", **kwargs):
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assert len(i) == 1
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kwargs = dict(i=i, i_dw=1, o=o, o_dw=len(o), clk=clk, clkdiv=clkdiv,
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name=f"des_{name}".strip("_"), **kwargs)
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self.submodules += Deserializer(**kwargs)
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class SimLogger(Module, AutoCSR):
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"""Logger for use in simulation
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