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phy/usddrphy: cleanup primitives instances

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This commit is contained in:
Florent Kermarrec 2020-01-26 12:44:48 +01:00
parent 33c5d7b87e
commit 72da321fa4
1 changed files with 245 additions and 174 deletions
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419
litedram/phy/usddrphy.py
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@ -18,8 +18,12 @@ from litedram.phy.dfi import *
# Xilinx Ultrascale DDR3/DDR4 PHY ------------------------------------------------------------------
class USDDRPHY(Module, AutoCSR):
def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6, iodelay_clk_freq=200e6, cmd_latency=0):
tck = 2/(2*4*sys_clk_freq)
def __init__(self, pads,
memtype = "DDR3",
sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6,
cmd_latency = 0):
tck = 2/(2*4*sys_clk_freq)
addressbits = len(pads.a)
if memtype == "DDR4":
addressbits += 3 # cas_n/ras_n/we_n multiplexed with address
@ -92,29 +96,35 @@ class USDDRPHY(Module, AutoCSR):
clk_o_delayed = Signal()
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=clk_o_nodelay,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=0b10101010
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = clk_o_nodelay,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D = 0b10101010
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=clk_o_nodelay, o_DATAOUT=clk_o_delayed
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._cdly_rst.re,
i_CE = self._cdly_inc.re,
i_ODATAIN = clk_o_nodelay,
o_DATAOUT = clk_o_delayed
),
Instance("OBUFDS",
i_I=clk_o_delayed,
o_O=pads.clk_p,
o_OB=pads.clk_n
i_I = clk_o_delayed,
o_O = pads.clk_p,
o_OB = pads.clk_n
)
]
@ -123,27 +133,34 @@ class USDDRPHY(Module, AutoCSR):
a_o_nodelay = Signal()
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=a_o_nodelay,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=Cat(dfi.phases[0].address[i], dfi.phases[0].address[i],
dfi.phases[1].address[i], dfi.phases[1].address[i],
dfi.phases[2].address[i], dfi.phases[2].address[i],
dfi.phases[3].address[i], dfi.phases[3].address[i])
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = a_o_nodelay,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(dfi.phases[0].address[i], dfi.phases[0].address[i],
dfi.phases[1].address[i], dfi.phases[1].address[i],
dfi.phases[2].address[i], dfi.phases[2].address[i],
dfi.phases[3].address[i], dfi.phases[3].address[i])
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=a_o_nodelay, o_DATAOUT=pads.a[i]
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._cdly_rst.re,
i_CE = self._cdly_inc.re,
i_ODATAIN = a_o_nodelay,
o_DATAOUT = pads.a[i]
)
]
@ -157,27 +174,35 @@ class USDDRPHY(Module, AutoCSR):
ba_o_nodelay = Signal()
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=ba_o_nodelay,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=Cat(dfi.phases[0].bank[i], dfi.phases[0].bank[i],
dfi.phases[1].bank[i], dfi.phases[1].bank[i],
dfi.phases[2].bank[i], dfi.phases[2].bank[i],
dfi.phases[3].bank[i], dfi.phases[3].bank[i])
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = ba_o_nodelay,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(
dfi.phases[0].bank[i], dfi.phases[0].bank[i],
dfi.phases[1].bank[i], dfi.phases[1].bank[i],
dfi.phases[2].bank[i], dfi.phases[2].bank[i],
dfi.phases[3].bank[i], dfi.phases[3].bank[i])
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=ba_o_nodelay, o_DATAOUT=pads_ba[i]
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._cdly_rst.re,
i_CE = self._cdly_inc.re,
i_ODATAIN = ba_o_nodelay,
o_DATAOUT = pads_ba[i]
)
]
@ -192,32 +217,40 @@ class USDDRPHY(Module, AutoCSR):
x_o_nodelay = Signal()
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=x_o_nodelay,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=Cat(getattr(dfi.phases[0], name), getattr(dfi.phases[0], name),
getattr(dfi.phases[1], name), getattr(dfi.phases[1], name),
getattr(dfi.phases[2], name), getattr(dfi.phases[2], name),
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = x_o_nodelay,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(
getattr(dfi.phases[0], name), getattr(dfi.phases[0], name),
getattr(dfi.phases[1], name), getattr(dfi.phases[1], name),
getattr(dfi.phases[2], name), getattr(dfi.phases[2], name),
getattr(dfi.phases[3], name), getattr(dfi.phases[3], name))
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=x_o_nodelay, o_DATAOUT=getattr(pads, name)
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._cdly_rst.re,
i_CE = self._cdly_inc.re,
i_ODATAIN = x_o_nodelay,
o_DATAOUT = getattr(pads, name)
)
]
# DQS and DM -------------------------------------------------------------------------------
oe_dqs = Signal()
oe_dqs = Signal()
dqs_serdes_pattern = Signal(8)
self.comb += \
If(self._wlevel_en.storage,
@ -231,42 +264,51 @@ class USDDRPHY(Module, AutoCSR):
)
for i in range(databits//8):
dm_o_nodelay = Signal()
self.specials += \
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=dm_o_nodelay,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=Cat(dfi.phases[0].wrdata_mask[i], dfi.phases[0].wrdata_mask[databits//8+i],
dfi.phases[1].wrdata_mask[i], dfi.phases[1].wrdata_mask[databits//8+i],
dfi.phases[2].wrdata_mask[i], dfi.phases[2].wrdata_mask[databits//8+i],
dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i])
)
self.specials += \
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = dm_o_nodelay,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(
dfi.phases[0].wrdata_mask[i], dfi.phases[0].wrdata_mask[databits//8+i],
dfi.phases[1].wrdata_mask[i], dfi.phases[1].wrdata_mask[databits//8+i],
dfi.phases[2].wrdata_mask[i], dfi.phases[2].wrdata_mask[databits//8+i],
dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i])
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._dly_sel.storage[i] & self._wdly_dq_rst.re,
i_CE=self._dly_sel.storage[i] & self._wdly_dq_inc.re,
i_ODATAIN=dm_o_nodelay, o_DATAOUT=pads.dm[i]
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED = 0,
p_IS_RST_INVERTED = 0,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._dly_sel.storage[i] & self._wdly_dq_rst.re,
i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re,
i_ODATAIN = dm_o_nodelay,
o_DATAOUT = pads.dm[i]
)
]
dqs_nodelay = Signal()
dqs_delayed = Signal()
dqs_t = Signal()
dqs_t = Signal()
if i == 0:
# Store initial DQS DELAY_VALUE (in taps) to be able to reload DELAY_VALUE after reset.
dqs_taps = Signal(9)
dqs_taps = Signal(9)
dqs_taps_timer = WaitTimer(2**16)
dqs_taps_done = Signal()
self.submodules += dqs_taps_timer
dqs_taps_done = Signal()
self.comb += dqs_taps_timer.wait.eq(~dqs_taps_done)
self.sync += \
If(dqs_taps_timer.done,
@ -275,34 +317,47 @@ class USDDRPHY(Module, AutoCSR):
)
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = dqs_nodelay,
o_T_OUT = dqs_t,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_T = ~oe_dqs,
i_D = Cat(
dqs_serdes_pattern[0], dqs_serdes_pattern[1],
dqs_serdes_pattern[2], dqs_serdes_pattern[3],
dqs_serdes_pattern[4], dqs_serdes_pattern[5],
dqs_serdes_pattern[6], dqs_serdes_pattern[7]),
o_OQ=dqs_nodelay, o_T_OUT=dqs_t,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=Cat(dqs_serdes_pattern[0], dqs_serdes_pattern[1],
dqs_serdes_pattern[2], dqs_serdes_pattern[3],
dqs_serdes_pattern[4], dqs_serdes_pattern[5],
dqs_serdes_pattern[6], dqs_serdes_pattern[7]),
i_T=~oe_dqs,
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=int(tck*1e12/4),
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._dly_sel.storage[i] & self._wdly_dqs_rst.re,
i_CE=self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
o_CNTVALUEOUT=Signal(9) if i != 0 else dqs_taps,
i_ODATAIN=dqs_nodelay, o_DATAOUT=dqs_delayed
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED = 0,
p_IS_RST_INVERTED = 0,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = int(tck*1e12/4),
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._dly_sel.storage[i] & self._wdly_dqs_rst.re,
i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
o_CNTVALUEOUT = Signal(9) if i != 0 else dqs_taps,
i_ODATAIN = dqs_nodelay,
o_DATAOUT = dqs_delayed
),
Instance("IOBUFDSE3",
i_I=dqs_delayed, i_T=dqs_t,
io_IO=pads.dqs_p[i], io_IOB=pads.dqs_n[i]
i_I = dqs_delayed,
i_T = dqs_t,
io_IO = pads.dqs_p[i],
io_IOB = pads.dqs_n[i]
)
]
@ -313,8 +368,8 @@ class USDDRPHY(Module, AutoCSR):
dq_o_delayed = Signal()
dq_i_nodelay = Signal()
dq_i_delayed = Signal()
dq_t = Signal()
dq_bitslip = BitSlip(8)
dq_t = Signal()
dq_bitslip = BitSlip(8)
self.sync += \
If(self._dly_sel.storage[i//8],
If(self._rdly_dq_bitslip_rst.re,
@ -326,59 +381,75 @@ class USDDRPHY(Module, AutoCSR):
self.submodules += dq_bitslip
self.specials += [
Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=dq_o_nodelay, o_T_OUT=dq_t,
i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D=Cat(dfi.phases[0].wrdata[i], dfi.phases[0].wrdata[databits+i],
dfi.phases[1].wrdata[i], dfi.phases[1].wrdata[databits+i],
dfi.phases[2].wrdata[i], dfi.phases[2].wrdata[databits+i],
dfi.phases[3].wrdata[i], dfi.phases[3].wrdata[databits+i]),
i_T=~oe_dq
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
p_IS_RST_INVERTED = 0,
o_OQ = dq_o_nodelay,
o_T_OUT = dq_t,
i_RST = ResetSignal(),
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(
dfi.phases[0].wrdata[i], dfi.phases[0].wrdata[databits+i],
dfi.phases[1].wrdata[i], dfi.phases[1].wrdata[databits+i],
dfi.phases[2].wrdata[i], dfi.phases[2].wrdata[databits+i],
dfi.phases[3].wrdata[i], dfi.phases[3].wrdata[databits+i]),
i_T = ~oe_dq
),
Instance("ISERDESE3",
p_IS_CLK_INVERTED=0,
p_IS_CLK_B_INVERTED=1,
p_DATA_WIDTH=8,
i_D=dq_i_delayed,
i_RST=ResetSignal(),
i_FIFO_RD_EN=0,
i_CLK=ClockSignal("sys4x"),
i_CLK_B=ClockSignal("sys4x"), # locally inverted
i_CLKDIV=ClockSignal(),
o_Q=dq_bitslip.i
p_IS_CLK_INVERTED = 0,
p_IS_CLK_B_INVERTED = 1,
p_DATA_WIDTH = 8,
i_D = dq_i_delayed,
i_RST = ResetSignal(),
i_FIFO_RD_EN = 0,
i_CLK = ClockSignal("sys4x"),
i_CLK_B = ClockSignal("sys4x"), # locally inverted
i_CLKDIV = ClockSignal(),
o_Q = dq_bitslip.i
),
Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._dly_sel.storage[i//8] & self._wdly_dq_rst.re,
i_CE=self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
i_ODATAIN=dq_o_nodelay, o_DATAOUT=dq_o_delayed
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED = 0,
p_IS_RST_INVERTED = 0,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._dly_sel.storage[i//8] & self._wdly_dq_rst.re,
i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
i_ODATAIN = dq_o_nodelay,
o_DATAOUT = dq_o_delayed
),
Instance("IDELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC",p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
p_DELAY_FORMAT="TIME", p_DELAY_SRC="IDATAIN",
p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(),
i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_RST=self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
i_IDATAIN=dq_i_nodelay, o_DATAOUT=dq_i_delayed
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_IS_CLK_INVERTED = 0,
p_IS_RST_INVERTED = 0,
p_DELAY_FORMAT = "TIME",
p_DELAY_SRC = "IDATAIN",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_CLK = ClockSignal(),
i_INC = 1,
i_EN_VTC = self._en_vtc.storage,
i_RST = self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
i_IDATAIN = dq_i_nodelay,
o_DATAOUT = dq_i_delayed
),
Instance("IOBUF",
i_I=dq_o_delayed, o_O=dq_i_nodelay, i_T=dq_t,
io_IO=pads.dq[i]
i_I = dq_o_delayed,
o_O = dq_i_nodelay,
i_T = dq_t,
io_IO = pads.dq[i]
)
]
self.comb += [