bench: add genesys2 bench.
This commit is contained in:
Florent Kermarrec
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37fb44f33e
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74205979bd
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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import argparse
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from migen import *
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from litex.boards.platforms import genesys2
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41J256M16
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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def platform_request_all(platform, name):
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from litex.build.generic_platform import ConstraintError
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r = []
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while True:
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try:
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r += [platform.request(name, len(r))]
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except ConstraintError:
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break
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if r == []:
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raise ValueError
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return r
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoCSR):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys_pll = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.main_pll = main_pll = S7PLL(speedgrade=-2)
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self.comb += main_pll.reset.eq(~platform.request("cpu_reset_n"))
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main_pll.register_clkin(platform.request("clk200"), 200e6)
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main_pll.create_clkout(self.cd_sys_pll, 200e6)
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main_pll.create_clkout(self.cd_clk200, 200e6)
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main_pll.expose_drp()
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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sys_clk_counter = Signal(32)
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self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
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self.sys_clk_counter = CSRStatus(32)
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self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
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self.submodules.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(~main_pll.locked)
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pll.register_clkin(self.cd_sys_pll.clk, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6)):
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platform = genesys2.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size = 0x8000,
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csr_data_width = 32,
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uart_name = "crossover")
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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cmd_latency = 1)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J256M16(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"]
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)
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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with_hw_init_reset = False)
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.submodules.led = LedChaser(Cat(platform_request_all(platform, "user_led")), sys_clk_freq)
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self.add_csr("led")
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# Bench Test ---------------------------------------------------------------------------------------
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def bench_test():
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import time
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from litex import RemoteClient
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wb = RemoteClient()
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wb.open()
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# # #
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class ClkReg1:
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def __init__(self, value=0):
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self.unpack(value)
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def unpack(self, value):
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self.low_time = (value >> 0) & (2**6 - 1)
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self.high_time = (value >> 6) & (2**6 - 1)
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self.reserved = (value >> 12) & (2**1 - 1)
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self.phase_mux = (value >> 13) & (2**3 - 1)
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def pack(self):
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value = (self.low_time << 0)
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value |= (self.high_time << 6)
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value |= (self.reserved << 12)
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value |= (self.phase_mux << 13)
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return value
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def __repr__(self):
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s = "ClkReg1:\n"
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s += " low_time: {:d}\n".format(self.low_time)
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s += " high_time: {:d}\n".format(self.high_time)
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s += " reserved: {:d}\n".format(self.reserved)
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s += " phase_mux: {:d}".format(self.phase_mux)
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return s
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class ClkReg2:
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def __init__(self, value = 0):
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self.unpack(value)
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def unpack(self, value):
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self.delay_time = (value >> 0) & (2**6 - 1)
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self.no_count = (value >> 6) & (2**1 - 1)
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self.edge = (value >> 7) & (2**1 - 1)
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self.mx = (value >> 8) & (2**2 - 1)
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self.frac_wf_r = (value >> 10) & (2**1 - 1)
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self.frac_en = (value >> 11) & (2**1 - 1)
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self.frac = (value >> 12) & (2**3 - 1)
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self.reserved = (value >> 15) & (2**1 - 1)
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def pack(self):
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value = (self.delay_time << 0)
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value |= (self.no_count << 6)
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value |= (self.edge << 7)
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value |= (self.mx << 8)
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value |= (self.frac_wf_r << 10)
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value |= (self.frac_en << 11)
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value |= (self.frac << 12)
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value |= (self.reserved << 15)
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return value
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def __repr__(self):
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s = "ClkReg2:\n"
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s += " delay_time: {:d}\n".format(self.delay_time)
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s += " no_count: {:d}\n".format(self.no_count)
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s += " edge: {:d}\n".format(self.edge)
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s += " mx: {:d}\n".format(self.mx)
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s += " frac_wf_r: {:d}\n".format(self.frac_wf_r)
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s += " frac_en: {:d}\n".format(self.frac_en)
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s += " frac: {:d}\n".format(self.frac)
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s += " reserved: {:d}".format(self.reserved)
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return s
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class S7PLL:
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def reset(self):
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wb.regs.crg_main_pll_drp_reset.write(1)
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def read(self, adr):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_read.write(1)
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return wb.regs.crg_main_pll_drp_dat_r.read()
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def write(self, adr, value):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_dat_w.write(value)
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wb.regs.crg_main_pll_drp_write.write(1)
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# # #
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vco_freq = 1.8e9
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s7pll = S7PLL()
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print("Dump Main PLL...")
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x08))
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print(clkout0_clkreg1)
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for i in range(7, 14):
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sys_clk_freq = (125e6/200e6)*(vco_freq/i)
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print("Reconfig Main PLL to {}MHz...".format(sys_clk_freq/1e6))
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clkout0_clkreg1.high_time = i//2 + i%2
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clkout0_clkreg1.low_time = i//2
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s7pll.write(0x08, clkout0_clkreg1.pack())
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print("Measuring sys_clk...")
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duration = 5e-1
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start = wb.regs.crg_sys_clk_counter.read()
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time.sleep(duration)
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end = wb.regs.crg_sys_clk_counter.read()
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print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration)))
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print("Reset SoC and get BIOS log...")
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wb.regs.ctrl_reset.write(1)
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start = time.time()
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while (time.time() - start) < 5:
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if wb.regs.uart_xover_rxempty.read() == 0:
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print("{:c}".format(wb.regs.uart_xover_rxtx.read()), end="")
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# # #
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wb.close()
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# Main ---------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Bench on Genesys2")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--test", action="store_true", help="Run Test")
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args = parser.parse_args()
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if args.build or args.load:
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.test:
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bench_test()
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if __name__ == "__main__":
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main()
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