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401554f94c
commit
746329cb43
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@ -75,7 +75,7 @@ def get_lpddr_phy_init_sequence(phy_settings, timing_settings):
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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return init_sequence, mr1
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return init_sequence, None
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# DDR2 ---------------------------------------------------------------------------------------------
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def get_ddr2_phy_init_sequence(phy_settings, timing_settings):
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