phy/usddrphy: add Ultrascale Plus support.
Similar to Ultrascale, but SIM_DEVICE needs to be changes to "ULTRASCALE_PLUS".
This commit is contained in:
Florent Kermarrec
parent
b8339886da
commit
752e006cf9
4
README
4
README
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@ -3,7 +3,7 @@
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/ /__/ / __/ -_) // / , _/ __ |/ /|_/ /
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/____/_/\__/\__/____/_/|_/_/ |_/_/ /_/
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Copyright 2015-2019 / EnjoyDigital
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Copyright 2015-2020 / EnjoyDigital
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A small footprint and configurable DRAM core
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powered by Migen & LiteX
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@ -27,7 +27,7 @@ PHY:
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- Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
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- Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
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- Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
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- Kintex/Virtex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio)
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- Kintex/Virtex Ultrascale (Plus) DDR3/DDR4 PHY (1:4 frequency ratio)
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- ECP5 DDR3 PHY (1:2 frequency ratio)
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Core:
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- Fully pipelined, high performance.
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@ -1,7 +1,7 @@
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# 1:4 frequency-ratio DDR3/DDR4 PHY for Kintex/Virtex Ultrascale
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# 1:4 frequency-ratio DDR3/DDR4 PHY for Kintex/Virtex Ultrascale (Plus)
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# DDR3: 800, 1066, 1333 and 1600 MT/s
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# DDR4: 1600 MT/s
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@ -15,14 +15,15 @@ from litex.soc.interconnect.csr import *
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from litedram.common import *
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from litedram.phy.dfi import *
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# Xilinx Ultrascale DDR3/DDR4 PHY ------------------------------------------------------------------
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# Xilinx Ultrascale (Plus) DDR3/DDR4 PHY -----------------------------------------------------------
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class USDDRPHY(Module, AutoCSR):
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def __init__(self, pads,
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memtype = "DDR3",
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sys_clk_freq = 100e6,
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iodelay_clk_freq = 200e6,
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cmd_latency = 0):
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cmd_latency = 0,
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sim_device = "ULTRASCALE"):
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tck = 2/(2*4*sys_clk_freq)
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addressbits = len(pads.a)
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if memtype == "DDR4":
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@ -32,6 +33,7 @@ class USDDRPHY(Module, AutoCSR):
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databits = len(pads.dq)
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nphases = 4
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assert databits%8 == 0
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assert sim_device in ["ULTRASCALE", "ULTRASCALE_PLUS"]
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if hasattr(pads, "ten"):
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self.comb += pads.ten.eq(0)
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@ -96,6 +98,7 @@ class USDDRPHY(Module, AutoCSR):
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clk_o_delayed = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -108,6 +111,7 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ = clk_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -134,6 +138,7 @@ class USDDRPHY(Module, AutoCSR):
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a_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -149,6 +154,7 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ = a_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -175,6 +181,7 @@ class USDDRPHY(Module, AutoCSR):
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ba_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -191,6 +198,7 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ = ba_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -218,6 +226,7 @@ class USDDRPHY(Module, AutoCSR):
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x_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -234,6 +243,7 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ = x_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -266,6 +276,7 @@ class USDDRPHY(Module, AutoCSR):
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dm_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -282,6 +293,7 @@ class USDDRPHY(Module, AutoCSR):
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o_OQ = dm_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -317,6 +329,7 @@ class USDDRPHY(Module, AutoCSR):
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)
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -336,6 +349,7 @@ class USDDRPHY(Module, AutoCSR):
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -381,6 +395,7 @@ class USDDRPHY(Module, AutoCSR):
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self.submodules += dq_bitslip
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = sim_device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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@ -399,6 +414,7 @@ class USDDRPHY(Module, AutoCSR):
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o_T_OUT = dq_t,
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),
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Instance("ISERDESE3",
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p_SIM_DEVICE = sim_device,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLK_B_INVERTED = 1,
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p_DATA_WIDTH = 8,
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@ -411,6 +427,7 @@ class USDDRPHY(Module, AutoCSR):
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o_Q = dq_bitslip.i,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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@ -428,6 +445,7 @@ class USDDRPHY(Module, AutoCSR):
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o_DATAOUT = dq_o_delayed,
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),
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Instance("IDELAYE3",
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p_SIM_DEVICE = sim_device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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