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phy/ecp5ddrphy: Bring back dm_remapping 

This allows swapping UDM/LDM pins. Was removed in
af9abd6ec9
 phy/ecp5ddrphy: remove dm_remapping introduce for VexRiscv-SMP on OrangeCrab...

But is still useful for native port uses of litedram

Add dm_swap parameter to gen.py

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
This commit is contained in:
Matt Johnston 2021-11-17 15:01:36 +08:00
parent 06ca898c69
commit 7560435d07
2 changed files with 11 additions and 3 deletions
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7
litedram/gen.py
View File

@ -582,10 +582,15 @@ class LiteDRAMCore(SoCCore):
# ECP5DDRPHY. # ECP5DDRPHY.
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
assert core_config["memtype"] in ["DDR3"] assert core_config["memtype"] in ["DDR3"]
kwargs = {}
if core_config.get("dm_swap", False):
kwargs['dm_remapping'] = {0:1, 1:0}
self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"]( self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"](
pads = platform.request("ddram"), pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
cmd_delay = core_config.get("cmd_delay", 0)) cmd_delay = core_config.get("cmd_delay", 0),
**kwargs)
self.ddrphy.settings.add_electrical_settings(**electrical_settings_kwargs) self.ddrphy.settings.add_electrical_settings(**electrical_settings_kwargs)
self.comb += crg.stop.eq(self.ddrphy.init.stop) self.comb += crg.stop.eq(self.ddrphy.init.stop)
self.comb += crg.reset.eq(self.ddrphy.init.reset) self.comb += crg.reset.eq(self.ddrphy.init.reset)

7
litedram/phy/ecp5ddrphy.py
View File

@ -117,7 +117,8 @@ class ECP5DDRPHY(Module, AutoCSR):
cl = None, cl = None,
cwl = None, cwl = None,
cmd_delay = 0, cmd_delay = 0,
clk_polarity = 0): clk_polarity = 0,
dm_remapping = None):
assert isinstance(cmd_delay, int) and cmd_delay < 128 assert isinstance(cmd_delay, int) and cmd_delay < 128
pads = PHYPadsCombiner(pads) pads = PHYPadsCombiner(pads)
memtype = "DDR3" memtype = "DDR3"
@ -127,6 +128,8 @@ class ECP5DDRPHY(Module, AutoCSR):
nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n) nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
databits = len(pads.dq) databits = len(pads.dq)
nphases = 2 nphases = 2
if not dm_remapping:
dm_remapping = {}
assert databits%8 == 0 assert databits%8 == 0
# Init ------------------------------------------------------------------------------------- # Init -------------------------------------------------------------------------------------
@ -327,7 +330,7 @@ class ECP5DDRPHY(Module, AutoCSR):
dm_o_data_d = Signal(8) dm_o_data_d = Signal(8)
dm_o_data_muxed = Signal(4) dm_o_data_muxed = Signal(4)
for n in range(8): for n in range(8):
self.comb += dm_o_data[n].eq(dfi.phases[n//4].wrdata_mask[n%4*databits//8 + i]) self.comb += dm_o_data[n].eq(dfi.phases[n//4].wrdata_mask[n%4*databits//8+dm_remapping.get(i, i)])
self.sync += dm_o_data_d.eq(dm_o_data) self.sync += dm_o_data_d.eq(dm_o_data)
dm_bl8_cases = {} dm_bl8_cases = {}
dm_bl8_cases[0] = dm_o_data_muxed.eq(dm_o_data[:4]) dm_bl8_cases[0] = dm_o_data_muxed.eq(dm_o_data[:4])