modules: add MT41J256M16

2017-03-14 20:59:02 +01:00 · 2017-03-14 20:59:02 +01:00 · 767b0144eb
parent ddb05b92b6
commit 767b0144eb
1 changed files with 15 additions and 0 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -203,3 +203,18 @@ class MT41K256M16(SDRAMModule):
    tWTR  = 8
    tREFI = 64*1000*1000/8192
    tRFC  = 260
+
+
+class MT41J256M16(SDRAMModule):
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 32768
+    ncols  = 1024
+    # timings (-125 speedgrade)
+    tRP   = 13.75
+    tRCD  = 13.75
+    tWR   = 15
+    tWTR  = 8
+    tREFI = 64*1000*1000/8192
+    tRFC  = 260