test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation
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@ -22,10 +22,12 @@ except ImportError as e:
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_summary = False
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print('[WARNING] Results summary not available:', e, file=sys.stderr)
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from litex.tools.litex_sim import get_sdram_phy_settings, sdram_module_nphases
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from litedram import modules as litedram_modules
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from litedram.common import Settings as _Settings
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from . import benchmark
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from .benchmark import LiteDRAMBenchmarkSoC, load_access_pattern
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from .benchmark import load_access_pattern
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# Benchmark configuration --------------------------------------------------------------------------
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@ -121,21 +123,17 @@ class BenchmarkConfiguration(Settings):
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return 'BenchmarkConfiguration(%s)' % self.as_dict()
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@property
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def soc(self):
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if not hasattr(self, '_soc'):
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kwargs = dict(
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sdram_module=self.sdram_module,
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sdram_data_width=self.sdram_data_width,
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)
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if isinstance(self.access_pattern, GeneratedAccess):
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kwargs['bist_length'] = self.access_pattern.bist_length
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kwargs['bist_random'] = self.access_pattern.bist_random
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elif isinstance(self.access_pattern, CustomAccess):
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kwargs['pattern_init'] = self.access_pattern.pattern
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else:
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raise ValueError(self.access_pattern)
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self._soc = LiteDRAMBenchmarkSoC(**kwargs)
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return self._soc
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def sdram_clk_freq(self):
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return 100e6 # FIXME: value of 100MHz is hardcoded in litex_sim
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@property
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def sdram_controller_data_width(self):
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# use values from module class (no need to instantiate it)
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sdram_module_cls = getattr(litedram_modules, self.sdram_module)
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memtype = sdram_module_cls.memtype
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nphases = sdram_module_nphases[memtype]
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dfi_databits = self.sdram_data_width * (1 if memtype == 'SDR' else 2)
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return dfi_databits * nphases
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# Benchmark results --------------------------------------------------------------------------------
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@ -224,8 +222,8 @@ class ResultsSummary:
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'generator_ticks': lambda d: d.result.generator_ticks,
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'checker_errors': lambda d: d.result.checker_errors,
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'checker_ticks': lambda d: d.result.checker_ticks,
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'ctrl_data_width': lambda d: d.config.soc.sdram.controller.interface.data_width,
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'clk_freq': lambda d: d.config.soc.sdrphy.module.clk_freq,
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'ctrl_data_width': lambda d: d.config.sdram_controller_data_width,
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'clk_freq': lambda d: d.config.sdram_clk_freq,
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}
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columns = {name: [mapping(data) for data in run_data] for name, mapping, in column_mappings.items()}
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self.df = df = pd.DataFrame(columns)
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