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test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation

This commit is contained in:
Jędrzej Boczar 2020-02-06 14:21:35 +01:00
parent 027034db49
commit 77541c3670
1 changed files with 16 additions and 18 deletions
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34
test/run_benchmarks.py
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@ -22,10 +22,12 @@ except ImportError as e:
_summary = False _summary = False
print('[WARNING] Results summary not available:', e, file=sys.stderr) print('[WARNING] Results summary not available:', e, file=sys.stderr)
from litex.tools.litex_sim import get_sdram_phy_settings, sdram_module_nphases
from litedram import modules as litedram_modules
from litedram.common import Settings as _Settings from litedram.common import Settings as _Settings
from . import benchmark from . import benchmark
from .benchmark import LiteDRAMBenchmarkSoC, load_access_pattern from .benchmark import load_access_pattern
# Benchmark configuration -------------------------------------------------------------------------- # Benchmark configuration --------------------------------------------------------------------------
@ -121,21 +123,17 @@ class BenchmarkConfiguration(Settings):
return 'BenchmarkConfiguration(%s)' % self.as_dict() return 'BenchmarkConfiguration(%s)' % self.as_dict()
@property @property
def soc(self): def sdram_clk_freq(self):
if not hasattr(self, '_soc'): return 100e6 # FIXME: value of 100MHz is hardcoded in litex_sim
kwargs = dict(
sdram_module=self.sdram_module, @property
sdram_data_width=self.sdram_data_width, def sdram_controller_data_width(self):
) # use values from module class (no need to instantiate it)
if isinstance(self.access_pattern, GeneratedAccess): sdram_module_cls = getattr(litedram_modules, self.sdram_module)
kwargs['bist_length'] = self.access_pattern.bist_length memtype = sdram_module_cls.memtype
kwargs['bist_random'] = self.access_pattern.bist_random nphases = sdram_module_nphases[memtype]
elif isinstance(self.access_pattern, CustomAccess): dfi_databits = self.sdram_data_width * (1 if memtype == 'SDR' else 2)
kwargs['pattern_init'] = self.access_pattern.pattern return dfi_databits * nphases
else:
raise ValueError(self.access_pattern)
self._soc = LiteDRAMBenchmarkSoC(**kwargs)
return self._soc
# Benchmark results -------------------------------------------------------------------------------- # Benchmark results --------------------------------------------------------------------------------
@ -224,8 +222,8 @@ class ResultsSummary:
'generator_ticks': lambda d: d.result.generator_ticks, 'generator_ticks': lambda d: d.result.generator_ticks,
'checker_errors': lambda d: d.result.checker_errors, 'checker_errors': lambda d: d.result.checker_errors,
'checker_ticks': lambda d: d.result.checker_ticks, 'checker_ticks': lambda d: d.result.checker_ticks,
'ctrl_data_width': lambda d: d.config.soc.sdram.controller.interface.data_width, 'ctrl_data_width': lambda d: d.config.sdram_controller_data_width,
'clk_freq': lambda d: d.config.soc.sdrphy.module.clk_freq, 'clk_freq': lambda d: d.config.sdram_clk_freq,
} }
columns = {name: [mapping(data) for data in run_data] for name, mapping, in column_mappings.items()} columns = {name: [mapping(data) for data in run_data] for name, mapping, in column_mappings.items()}
self.df = df = pd.DataFrame(columns) self.df = df = pd.DataFrame(columns)