litedram/frontend/adapter.py rewrite up converter to optimize for bandwidth
This change is necessary to run litevideo, as old up converter was too slow to support high bandwidth requirements of HDMI core. Also old upconverter had two bugs: * reading sequentially and non-sequentially would return data in the same order * writing sequentailly and non-sequentially would return different memory state test/test_adapter.py add new up converter test: test_up_converter_writes_not_sequential This test checks if non-sequential writes to one dram word will create the same result as sequential writes Add parameters for rx_buffer, tx_buffer and cmd_buffer depths Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
This commit is contained in:
parent
3d066c87f9
commit
7b3c6abd50
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@ -76,7 +76,8 @@ class LiteDRAMCrossbar(Module):
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self.masters = []
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def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False):
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def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False,
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rx_buffer_depth=4, tx_buffer_depth=4, cmd_buffer_depth=4, priority=0):
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if self.finalized:
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raise FinalizeError
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@ -117,7 +118,8 @@ class LiteDRAMCrossbar(Module):
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clock_domain = clock_domain,
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id = port.id)
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self.submodules += ClockDomainsRenamer(clock_domain)(
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LiteDRAMNativePortConverter(new_port, port, reverse))
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LiteDRAMNativePortConverter(new_port, port, reverse,
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rx_buffer_depth, tx_buffer_depth, cmd_buffer_depth))
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port = new_port
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return port
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@ -22,9 +22,9 @@ class LiteDRAMNativePortCDC(Module):
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assert port_from.data_width == port_to.data_width
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assert port_from.mode == port_to.mode
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address_width = port_from.address_width
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data_width = port_from.data_width
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mode = port_from.mode
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address_width = port_from.address_width
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data_width = port_from.data_width
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mode = port_from.mode
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# # #
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@ -81,6 +81,7 @@ class LiteDRAMNativePortDownConverter(Module):
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ratio = port_from.data_width//port_to.data_width
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mode = port_from.mode
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count = Signal(max=ratio)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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@ -96,7 +97,7 @@ class LiteDRAMNativePortDownConverter(Module):
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port_to.cmd.addr.eq(port_from.cmd.addr*ratio + count),
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If(port_to.cmd.ready,
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NextValue(count, count + 1),
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If(count == (ratio - 1),
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If(count == ratio - 1,
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port_from.cmd.ready.eq(1),
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NextState("IDLE")
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)
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@ -136,7 +137,8 @@ class LiteDRAMNativePortUpConverter(Module):
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middle of a burst, but last command has to use cmd.last=1 if the last burst
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is not complete (not all N addresses have been used).
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"""
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def __init__(self, port_from, port_to, reverse=False):
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def __init__(self, port_from, port_to, reverse=False,
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rx_buffer_depth=4, tx_buffer_depth=4, cmd_buffer_depth=4):
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assert port_from.clock_domain == port_to.clock_domain
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assert port_from.data_width < port_to.data_width
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assert port_from.mode == port_to.mode
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@ -145,219 +147,419 @@ class LiteDRAMNativePortUpConverter(Module):
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# # #
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ratio = port_to.data_width//port_from.data_width
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mode = port_from.mode
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self.ratio = ratio = port_to.data_width//port_from.data_width
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mode = port_from.mode
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# Command ----------------------------------------------------------------------------------
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# Defines cmd type and the chunks that have been requested for the current port_to command.
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sel = Signal(ratio)
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cmd_buffer = stream.SyncFIFO([("sel", ratio), ("we", 1)], 0)
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self.submodules += cmd_buffer
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# Store last received command.
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cmd_addr = Signal.like(port_from.cmd.addr)
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# Defines read/write ordering of chunks that have been requested
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ordering_layout = [
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("counter", log2_int(ratio) + 1),
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("ordering", ratio * log2_int(ratio))
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]
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self.rx_buffer = rx_buffer = stream.SyncFIFO(ordering_layout, rx_buffer_depth)
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self.tx_buffer = tx_buffer = stream.SyncFIFO(ordering_layout, tx_buffer_depth)
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self.submodules += rx_buffer, tx_buffer
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# Store last received command
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cmd_addr = Signal.like(port_to.cmd.addr)
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cmd_we = Signal()
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cmd_last = Signal()
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# Indicates that we need to proceed to the next port_to command.
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next_cmd = Signal()
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# Indicates that we need to proceed to the next port_to command
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cmd_finished = Signal()
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addr_changed = Signal()
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# Signals that indicate that write/read convertion has finished.
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# Signals that indicate that write/read convertion has finished
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wdata_finished = Signal()
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rdata_finished = Signal()
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# Used to prevent reading old memory value if previous command has written the same address.
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read_lock = Signal()
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read_unlocked = Signal()
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rw_collision = Signal()
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# Different order depending on read/write:
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# - read: new -> cmd -> fill -> commit -> new
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# - write: new -> fill -> commit -> cmd -> new
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# For writes we have to send the command at the end to prevent situations when, during
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# a burst, LiteDRAM expects data (wdata_ready=1) but write converter is still converting.
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self.submodules.fsm = fsm = FSM()
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fsm.act("NEW",
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port_from.cmd.ready.eq(port_from.cmd.valid & ~read_lock),
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If(port_from.cmd.ready,
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NextValue(cmd_addr, port_from.cmd.addr),
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NextValue(cmd_we, port_from.cmd.we),
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NextValue(cmd_last, port_from.cmd.last),
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NextValue(sel, 1 << port_from.cmd.addr[:log2_int(ratio)]),
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If(port_from.cmd.we,
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NextState("FILL"),
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# Used to keep access order for reads and writes
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counter = Signal(log2_int(ratio) + 1)
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ordering = Signal(ratio * log2_int(ratio))
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# Send Command -----------------------------------------------------------------------------
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self.send_cmd = send_cmd = Signal()
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self.send_cmd_addr = send_cmd_addr = Signal.like(port_to.cmd.addr)
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self.send_cmd_we = send_cmd_we = Signal.like(port_to.cmd.we)
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self.send_cmd_busy = send_cmd_busy = Signal()
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send_inner_cmd_addr = Signal.like(port_to.cmd.addr)
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send_inner_cmd_we = Signal.like(port_to.cmd.we)
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self.cmd_buffer = cmd_buffer = stream.SyncFIFO([ ("cmd_addr", send_cmd_addr.nbits),
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("cmd_we", send_cmd_we.nbits)],
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cmd_buffer_depth)
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self.submodules += cmd_buffer
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self.comb += [
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send_cmd_busy.eq(~cmd_buffer.sink.ready),
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cmd_buffer.sink.valid.eq(send_cmd),
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cmd_buffer.sink.cmd_addr.eq(send_cmd_addr),
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cmd_buffer.sink.cmd_we.eq(send_cmd_we)
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]
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self.submodules.sender = send_fsm = FSM(reset_state="IDLE")
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send_fsm.act("IDLE",
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If(cmd_buffer.source.valid,
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cmd_buffer.source.ready.eq(1),
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NextValue(send_inner_cmd_addr, cmd_buffer.source.cmd_addr),
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NextValue(send_inner_cmd_we, cmd_buffer.source.cmd_we),
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NextState("SEND")
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)
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)
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send_fsm.act("SEND",
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port_to.cmd.valid.eq(1),
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port_to.cmd.addr.eq(send_inner_cmd_addr),
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port_to.cmd.we.eq(send_inner_cmd_we),
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If(port_to.cmd.ready,
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If(cmd_buffer.source.valid,
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cmd_buffer.source.ready.eq(1),
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NextValue(send_inner_cmd_addr, cmd_buffer.source.cmd_addr),
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NextValue(send_inner_cmd_we, cmd_buffer.source.cmd_we),
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NextState("SEND")
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).Else(
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NextState("CMD"),
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NextState("IDLE")
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)
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)
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)
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fsm.act("CMD",
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port_to.cmd.valid.eq(1),
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port_to.cmd.we.eq(cmd_we),
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port_to.cmd.addr.eq(cmd_addr[log2_int(ratio):]),
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If(port_to.cmd.ready,
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# Command flow is quite complicate, nonlinear and it depends on type read/write,
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# so here is summary:
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# This FSM receives commands from `port_from` and pushes them to `cmd_buffer` queue,
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# which is then handled by the `send_fsm` which sends commands to `port_to`.
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# In the FILL phase we gather the requested ordering of data chunks that map to a single
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# `port_to` transaction. The order of states in the FSM depends on command type: read
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# commands are queued on reception, write commands after the FILL phase.
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# Data order is also queued after FILL phase, at that point we know right order
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# Longer version
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# WAIT-FOR-CMD:
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# - if there is new cmd available do
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# - set internal variable
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# - check if it's read or write
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# - write: go to FILL
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# - read: try to send (queue) read cmd
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# - if successful goto FILL
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# - else goto WAIT-TO-SEND
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#
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# WAIT-TO-SEND:
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# - set cmd addr and cmd we to be sent (queued)
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# - if we can send (queue)
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# - if cmd was read goto FILL
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# - else
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# - if there is new cmd waiting and it's write goto FILL
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# - else goto WAIT-FOR-CMD
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# - else goto WAIT-TO-SEND
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#
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# FILL:
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# - if cmd finished
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# - if cmd was write do tx_commit
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# - else do rx_commit
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# - else
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# - acknowledged incoming cmds
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# - store their relative addresses (which subword of DRAM word)
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#
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# tx_commit(not a state, just combinational logic):
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# - try to store data ordering in tx_buffer
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# - if successful
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# - try to send (queue) cmd:
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# - if successful
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# - if there is new cmd and it's write
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# - set internal variables as in WAIT-FOR-CMD
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# - goto FILL
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# -else goto WAIT-FOR-CMD
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# - else goto WAIT_TO_SEND
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# - else goto WAIT-FOR-SPACE-IN-TX_BUFFER
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#
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# rx_commit(not a state, just combinational logic):
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# - try to store data ordering in rx_buffer
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# - if successful
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# - if there is new cmd and it's read
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# - set internal variables as in WAIT-FOR-CMD
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# - try to send (queue) cmd
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# - if successful
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# - acknowledge cmd
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# - store their relative address
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# - goto FILL
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# - else goto WAIT-TO-SEND
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# - else goto WAIT-FOR-CMD
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# - else goto WAIT-FOR-SPACE-IN-RX_BUFFER
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#
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# WAIT-FOR-SPACE-IN-TX_BUFFER:
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# - tx_commit
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#
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# WAIT-FOR-SPACE-IN-RX_BUFFER:
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# - rx_commit
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self.submodules.fsm = fsm = FSM(reset_state="WAIT-FOR-CMD")
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fsm.act("WAIT-FOR-CMD",
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If(port_from.cmd.valid,
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NextValue(counter, 0),
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NextValue(cmd_addr, port_from.cmd.addr[log2_int(ratio):]),
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NextValue(cmd_we, port_from.cmd.we),
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If(port_from.cmd.we,
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NextState("FILL")
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).Else(
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self.send_cmd.eq(1),
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self.send_cmd_addr.eq(port_from.cmd.addr[log2_int(ratio):]),
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self.send_cmd_we.eq(port_from.cmd.we),
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If(self.send_cmd_busy,
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NextState("WAIT-TO-SEND")
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).Else(
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NextState("FILL")
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)
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)
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)
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)
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fsm.act("WAIT-TO-SEND",
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send_cmd.eq(1),
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send_cmd_addr.eq(cmd_addr),
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send_cmd_we.eq(cmd_we),
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If(~send_cmd_busy,
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If(cmd_we,
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NextState("NEW")
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If(port_from.cmd.valid & port_from.cmd.we,
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NextValue(counter, 0),
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NextValue(cmd_addr, port_from.cmd.addr[log2_int(ratio):]),
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NextValue(cmd_we, port_from.cmd.we),
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NextState("FILL")
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).Else(
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NextState("WAIT-FOR-CMD")
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)
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).Else(
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NextState("FILL")
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)
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)
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)
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fsm.act("FILL",
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If(next_cmd,
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NextState("COMMIT")
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).Else( # Acknowledge incomming commands, while filling `sel`.
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port_from.cmd.ready.eq(port_from.cmd.valid),
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NextValue(cmd_last, port_from.cmd.last),
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If(port_from.cmd.valid,
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NextValue(sel, sel | 1 << port_from.cmd.addr[:log2_int(ratio)])
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)
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)
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)
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fsm.act("COMMIT",
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cmd_buffer.sink.valid.eq(1),
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cmd_buffer.sink.sel.eq(sel),
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cmd_buffer.sink.we.eq(cmd_we),
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If(cmd_buffer.sink.ready,
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If(cmd_we,
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NextState("CMD")
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).Else(
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NextState("NEW")
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)
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)
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)
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cases = {}
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for i in range(ratio):
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cases[i] = NextValue(ordering[i * log2_int(ratio) : (i + 1) * log2_int(ratio)],
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port_from.cmd.addr[:log2_int(ratio)])
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fsm.act("FILL",
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If(cmd_finished,
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If(cmd_we,
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self.tx_commit(cmd_addr, cmd_we, cmd_last, port_from, counter, ordering)
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).Else(
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self.rx_commit(cmd_addr, cmd_we, cmd_last, port_from, counter, ordering)
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)
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).Else(
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port_from.cmd.ready.eq(1),
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If(port_from.cmd.valid,
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NextValue(cmd_last, port_from.cmd.last),
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NextValue(counter, counter + 1),
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Case(counter, cases),
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)
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)
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)
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fsm.act("WAIT-FOR-SPACE-IN-RX_BUFFER",
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self.rx_commit(cmd_addr, cmd_we, cmd_last, port_from, counter, ordering)
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)
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fsm.act("WAIT-FOR-SPACE-IN-TX_BUFFER",
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self.tx_commit(cmd_addr, cmd_we, cmd_last, port_from, counter, ordering)
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)
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self.comb += [
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cmd_buffer.source.ready.eq(wdata_finished | rdata_finished),
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addr_changed.eq(cmd_addr[log2_int(ratio):] != port_from.cmd.addr[log2_int(ratio):]),
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# Collision happens on write to read transition when address does not change.
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rw_collision.eq(cmd_we & (port_from.cmd.valid & ~port_from.cmd.we) & ~addr_changed),
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tx_buffer.source.ready.eq(wdata_finished),
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rx_buffer.source.ready.eq(rdata_finished),
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addr_changed.eq(cmd_addr != port_from.cmd.addr[log2_int(ratio):]),
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# Go to the next command if one of the following happens:
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# - port_to address changes.
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# - cmd type changes.
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# - we received all the `ratio` commands.
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# - this is the last command in a sequence.
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# - master requests a flush (even after the command has been sent).
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next_cmd.eq(addr_changed | (cmd_we != port_from.cmd.we) | (sel == 2**ratio - 1)
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cmd_finished.eq(addr_changed | (cmd_we != port_from.cmd.we) | (counter == ratio)
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| cmd_last | port_from.flush),
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]
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self.sync += [
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# Block sending read command if we have just written to that address
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If(wdata_finished,
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read_lock.eq(0),
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read_unlocked.eq(1),
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).Elif(rw_collision & ~port_to.cmd.valid & ~read_unlocked,
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read_lock.eq(1)
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),
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If(port_from.cmd.valid & port_from.cmd.ready,
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read_unlocked.eq(0)
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)
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]
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# Read Datapath ----------------------------------------------------------------------------
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if mode in ["read", "both"]:
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# Queue received data not to loose it when it comes too fast.
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rdata_fifo = stream.SyncFIFO(port_to.rdata.description, ratio - 1)
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rdata_converter = stream.StrideConverter(
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description_from = port_to.rdata.description,
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description_to = port_from.rdata.description,
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reverse = reverse)
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self.submodules += rdata_fifo, rdata_converter
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read_upper_counter = Signal.like(counter)
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read_inner_counter = Signal.like(counter)
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read_inner_ordering = Signal.like(ordering)
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# Shift register with a bitmask of current chunk.
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rdata_chunk = Signal(ratio, reset=1)
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rdata_chunk_valid = Signal()
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self.sync += \
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If(rdata_converter.source.valid &
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rdata_converter.source.ready,
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rdata_chunk.eq(Cat(rdata_chunk[ratio-1], rdata_chunk[:ratio-1]))
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)
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read_chunk = Signal(log2_int(ratio))
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# Queue received data not to loose it when it comes too fast
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rdata_fifo = stream.SyncFIFO(port_to.rdata.description, cmd_buffer.depth + rx_buffer.depth + 1)
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self.submodules += rdata_fifo
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cases = {}
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for i in range(ratio):
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n = ratio-i-1 if reverse else i
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cases[i] = port_from.rdata.data.eq(rdata_fifo.source.data[
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n * port_from.data_width :(n + 1) * port_from.data_width]),
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self.comb += [
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# port_to -> rdata_fifo -> rdata_converter -> port_from
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# Port_to -> rdata_fifo -> order_mux -> port_from
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port_to.rdata.connect(rdata_fifo.sink),
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rdata_fifo.source.connect(rdata_converter.sink),
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rdata_chunk_valid.eq((cmd_buffer.source.sel & rdata_chunk) != 0),
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If(cmd_buffer.source.valid & ~cmd_buffer.source.we,
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# If that chunk is valid we send it to the user port and wait for ready.
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If(rdata_chunk_valid,
|
||||
port_from.rdata.valid.eq(rdata_converter.source.valid),
|
||||
port_from.rdata.data.eq(rdata_converter.source.data),
|
||||
rdata_converter.source.ready.eq(port_from.rdata.ready)
|
||||
).Else( # If this chunk was not requested in `sel`, ignore it.
|
||||
rdata_converter.source.ready.eq(1)
|
||||
),
|
||||
rdata_finished.eq(rdata_converter.source.valid & rdata_converter.source.ready
|
||||
& rdata_chunk[ratio - 1])
|
||||
rdata_fifo.source.ready.eq(rdata_finished),
|
||||
|
||||
If(rdata_fifo.source.valid & rx_buffer.source.valid,
|
||||
# If that chunk is valid we send it to the user port and wait for ready
|
||||
If(read_inner_counter < read_upper_counter,
|
||||
port_from.rdata.valid.eq(1),
|
||||
Case(read_chunk, cases),
|
||||
)
|
||||
)
|
||||
]
|
||||
|
||||
cases = {}
|
||||
for i in range(ratio):
|
||||
cases[i] = read_chunk.eq(read_inner_ordering[
|
||||
i * log2_int(ratio) : (i + 1) * log2_int(ratio)]),
|
||||
|
||||
self.comb += [
|
||||
# Select source of address order
|
||||
If(rx_buffer.source.valid,
|
||||
read_upper_counter.eq(rx_buffer.source.counter),
|
||||
read_inner_ordering.eq(rx_buffer.source.ordering)
|
||||
),
|
||||
# Select read chunk
|
||||
Case(read_inner_counter, cases),
|
||||
|
||||
rdata_finished.eq((read_inner_counter == read_upper_counter - 1) & rx_buffer.source.valid
|
||||
& (port_from.rdata.valid & port_from.rdata.ready))
|
||||
]
|
||||
|
||||
self.sync += [
|
||||
If(rdata_finished,
|
||||
read_inner_counter.eq(0)
|
||||
).Elif(port_from.rdata.valid & port_from.rdata.ready &
|
||||
(read_inner_counter < read_upper_counter),
|
||||
read_inner_counter.eq(read_inner_counter + 1)
|
||||
)
|
||||
]
|
||||
|
||||
# Write Datapath ---------------------------------------------------------------------------
|
||||
|
||||
if mode in ["write", "both"]:
|
||||
# Queue write data not to miss it when the lower chunks haven't been reqested.
|
||||
wdata_fifo = stream.SyncFIFO(port_from.wdata.description, ratio - 1)
|
||||
wdata_buffer = stream.SyncFIFO(port_to.wdata.description, 1)
|
||||
wdata_converter = stream.StrideConverter(
|
||||
description_from = port_from.wdata.description,
|
||||
description_to = port_to.wdata.description,
|
||||
reverse = reverse)
|
||||
self.submodules += wdata_converter, wdata_fifo, wdata_buffer
|
||||
write_upper_counter = Signal.like(counter)
|
||||
write_inner_counter = Signal.like(counter)
|
||||
write_inner_ordering = Signal.like(ordering)
|
||||
|
||||
# Shift register with a bitmask of current chunk.
|
||||
wdata_chunk = Signal(ratio, reset=1)
|
||||
wdata_chunk_valid = Signal()
|
||||
self.sync += \
|
||||
If(wdata_converter.sink.valid & wdata_converter.sink.ready,
|
||||
wdata_chunk.eq(Cat(wdata_chunk[ratio-1], wdata_chunk[:ratio-1]))
|
||||
)
|
||||
write_chunk = Signal(log2_int(ratio))
|
||||
|
||||
# Replicate `sel` bits to match the width of port_to.wdata.we.
|
||||
wdata_sel = Signal.like(port_to.wdata.we)
|
||||
if reverse:
|
||||
wdata_sel_parts = [
|
||||
Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
|
||||
for i in reversed(range(ratio))
|
||||
]
|
||||
else:
|
||||
wdata_sel_parts = [
|
||||
Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
|
||||
for i in range(ratio)
|
||||
]
|
||||
|
||||
self.sync += \
|
||||
If(cmd_buffer.source.valid & cmd_buffer.source.we & wdata_chunk[ratio - 1],
|
||||
wdata_sel.eq(Cat(wdata_sel_parts))
|
||||
)
|
||||
# Queue write data not to miss it when the lower chunks haven't been reqested
|
||||
wdata_fifo = stream.SyncFIFO(port_from.wdata.description, ratio)
|
||||
wdata_buffer = Record([("data", port_to.wdata.data.nbits),
|
||||
("we", port_to.wdata.we.nbits)])
|
||||
self.submodules += wdata_fifo
|
||||
|
||||
self.comb += [
|
||||
# port_from -> wdata_fifo -> wdata_converter
|
||||
# port_from -> wdata_fifo -> wdata_buffer (keeps order)
|
||||
port_from.wdata.connect(wdata_fifo.sink),
|
||||
wdata_buffer.source.connect(port_to.wdata),
|
||||
wdata_chunk_valid.eq((cmd_buffer.source.sel & wdata_chunk) != 0),
|
||||
If(cmd_buffer.source.valid & cmd_buffer.source.we,
|
||||
# When the current chunk is valid, read it from wdata_fifo.
|
||||
If(wdata_chunk_valid,
|
||||
wdata_converter.sink.valid.eq(wdata_fifo.source.valid),
|
||||
wdata_converter.sink.data.eq(wdata_fifo.source.data),
|
||||
wdata_converter.sink.we.eq(wdata_fifo.source.we),
|
||||
wdata_fifo.source.ready.eq(wdata_converter.sink.ready),
|
||||
).Else( # If chunk is not valid, send any data and do not advance fifo.
|
||||
wdata_converter.sink.valid.eq(1),
|
||||
),
|
||||
),
|
||||
wdata_buffer.sink.valid.eq(wdata_converter.source.valid),
|
||||
wdata_buffer.sink.data.eq(wdata_converter.source.data),
|
||||
wdata_buffer.sink.we.eq(wdata_converter.source.we & wdata_sel),
|
||||
wdata_converter.source.ready.eq(wdata_buffer.sink.ready),
|
||||
wdata_finished.eq(wdata_converter.sink.valid & wdata_converter.sink.ready
|
||||
& wdata_chunk[ratio-1]),
|
||||
port_to.wdata.data.eq(wdata_buffer.data),
|
||||
port_to.wdata.we.eq(wdata_buffer.we),
|
||||
port_to.wdata.valid.eq((write_inner_counter == write_upper_counter) & tx_buffer.source.valid),
|
||||
wdata_fifo.source.ready.eq(write_inner_counter < write_upper_counter),
|
||||
]
|
||||
|
||||
cases = {}
|
||||
for i in range(ratio):
|
||||
cases[i] = write_chunk.eq(write_inner_ordering[
|
||||
i * log2_int(ratio) : (i + 1) * log2_int(ratio)]),
|
||||
|
||||
self.comb += [
|
||||
# Select source of address order
|
||||
If(tx_buffer.source.valid,
|
||||
write_upper_counter.eq(tx_buffer.source.counter),
|
||||
write_inner_ordering.eq(tx_buffer.source.ordering)
|
||||
).Else(
|
||||
write_upper_counter.eq(counter),
|
||||
write_inner_ordering.eq(ordering)
|
||||
),
|
||||
|
||||
Case(write_inner_counter, cases),
|
||||
|
||||
wdata_finished.eq(port_to.wdata.valid & port_to.wdata.ready),
|
||||
]
|
||||
|
||||
cases = {}
|
||||
for i in range(ratio):
|
||||
n = ratio-i-1 if reverse else i
|
||||
cases[i] = [
|
||||
wdata_buffer.data[n * port_from.data_width : (n + 1) * port_from.data_width].eq(
|
||||
wdata_fifo.source.data),
|
||||
wdata_buffer.we[n * port_from.wdata.we.nbits : (n + 1) * port_from.wdata.we.nbits].eq(
|
||||
wdata_fifo.source.we),
|
||||
]
|
||||
|
||||
self.sync += [
|
||||
If(wdata_fifo.source.valid & wdata_fifo.source.ready,
|
||||
Case(write_chunk, cases)
|
||||
),
|
||||
If(wdata_finished,
|
||||
write_inner_counter.eq(0),
|
||||
wdata_buffer.we.eq(0),
|
||||
).Elif(wdata_fifo.source.valid & wdata_fifo.source.ready,
|
||||
write_inner_counter.eq(write_inner_counter + 1)
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
def tx_commit (self, cmd_addr, cmd_we, cmd_last, port_from, counter, ordering):
|
||||
return [
|
||||
self.tx_buffer.sink.valid.eq(1),
|
||||
self.tx_buffer.sink.counter.eq(counter),
|
||||
self.tx_buffer.sink.ordering.eq(ordering),
|
||||
If(self.tx_buffer.sink.ready,
|
||||
self.send_cmd.eq(1),
|
||||
self.send_cmd_addr.eq(cmd_addr),
|
||||
self.send_cmd_we.eq(cmd_we),
|
||||
If(self.send_cmd_busy,
|
||||
NextState("WAIT-TO-SEND")
|
||||
).Else(
|
||||
If(port_from.cmd.valid & port_from.cmd.we,
|
||||
NextValue(counter, 0),
|
||||
NextValue(cmd_addr, port_from.cmd.addr[log2_int(self.ratio):]),
|
||||
NextValue(cmd_we, port_from.cmd.we),
|
||||
NextState("FILL")
|
||||
).Else(
|
||||
NextState("WAIT-FOR-CMD")
|
||||
)
|
||||
)
|
||||
).Else(
|
||||
NextState("WAIT-FOR-SPACE-IN-TX_BUFFER")
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
def rx_commit (self, cmd_addr, cmd_we, cmd_last, port_from, counter, ordering):
|
||||
return [
|
||||
self.rx_buffer.sink.valid.eq(1),
|
||||
self.rx_buffer.sink.counter.eq(counter),
|
||||
self.rx_buffer.sink.ordering.eq(ordering),
|
||||
If(self.rx_buffer.sink.ready,
|
||||
If(port_from.cmd.valid & ~port_from.cmd.we,
|
||||
self.send_cmd.eq(1),
|
||||
self.send_cmd_addr.eq(port_from.cmd.addr[log2_int(self.ratio):]),
|
||||
self.send_cmd_we.eq(port_from.cmd.we),
|
||||
NextValue(cmd_addr, port_from.cmd.addr[log2_int(self.ratio):]),
|
||||
NextValue(cmd_we, port_from.cmd.we),
|
||||
If(self.send_cmd_busy,
|
||||
NextValue(counter, 0),
|
||||
NextState("WAIT-TO-SEND")
|
||||
).Else(
|
||||
port_from.cmd.ready.eq(1),
|
||||
NextValue(counter, 1),
|
||||
NextValue(ordering[:1 * log2_int(self.ratio)],
|
||||
port_from.cmd.addr[:log2_int(self.ratio)]),
|
||||
NextValue(cmd_last, port_from.cmd.last),
|
||||
NextState("FILL")
|
||||
)
|
||||
).Else(
|
||||
NextState("WAIT-FOR-CMD")
|
||||
)
|
||||
).Else(
|
||||
NextState("WAIT-FOR-SPACE-IN-RX_BUFFER")
|
||||
)
|
||||
]
|
||||
|
||||
# LiteDRAMNativePortConverter ----------------------------------------------------------------------
|
||||
|
||||
class LiteDRAMNativePortConverter(Module):
|
||||
def __init__(self, port_from, port_to, reverse=False):
|
||||
def __init__(self, port_from, port_to, reverse=False,
|
||||
rx_buffer_depth=4, tx_buffer_depth=4, cmd_buffer_depth=4):
|
||||
assert port_from.clock_domain == port_to.clock_domain
|
||||
assert port_from.mode == port_to.mode
|
||||
|
||||
|
@ -370,7 +572,9 @@ class LiteDRAMNativePortConverter(Module):
|
|||
self.submodules.converter = LiteDRAMNativePortDownConverter(port_from, port_to, reverse)
|
||||
elif ratio < 1:
|
||||
# UpConverter
|
||||
self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse)
|
||||
self.submodules.converter = LiteDRAMNativePortUpConverter(
|
||||
port_from, port_to, reverse,
|
||||
rx_buffer_depth, tx_buffer_depth, cmd_buffer_depth)
|
||||
else:
|
||||
# Identity
|
||||
self.comb += port_from.connect(port_to)
|
||||
|
|
|
@ -538,6 +538,30 @@ class MemoryTestDataMixin:
|
|||
0x00440000, # 0x1c
|
||||
]
|
||||
),
|
||||
"8bit_to_32bit_not_sequential": dict(
|
||||
pattern=[
|
||||
# address, data
|
||||
(0x03, 0x00),
|
||||
(0x02, 0x11),
|
||||
(0x01, 0x22),
|
||||
(0x00, 0x33),
|
||||
(0x12, 0x44),
|
||||
(0x11, 0x55),
|
||||
(0x13, 0x66),
|
||||
(0x10, 0x77),
|
||||
],
|
||||
expected=[
|
||||
# data, address
|
||||
0x00112233, # 0x00
|
||||
0x00000000, # 0x04
|
||||
0x00000000, # 0x08
|
||||
0x00000000, # 0x0c
|
||||
0x66445577, # 0x10
|
||||
0x00000000, # 0x14
|
||||
0x00000000, # 0x18
|
||||
0x00000000, # 0x1c
|
||||
]
|
||||
),
|
||||
"32bit_to_256bit": dict(
|
||||
pattern=[
|
||||
# address, data
|
||||
|
|
|
@ -22,6 +22,7 @@ from litex.gen.sim import *
|
|||
class ConverterDUT(Module):
|
||||
def __init__(self, user_data_width, native_data_width, mem_depth, separate_rw=True, read_latency=0):
|
||||
self.separate_rw = separate_rw
|
||||
|
||||
if separate_rw:
|
||||
self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=user_data_width)
|
||||
self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=native_data_width)
|
||||
|
@ -86,6 +87,7 @@ class TestAdapter(MemoryTestDataMixin, unittest.TestCase):
|
|||
dut.finalize()
|
||||
self.assertIn("ratio must be an int", str(cm.exception).lower())
|
||||
|
||||
|
||||
def test_up_converter_ratio_must_be_integer(self):
|
||||
with self.assertRaises(ValueError) as cm:
|
||||
dut = ConverterDUT(user_data_width=32, native_data_width=48, mem_depth=128)
|
||||
|
@ -339,6 +341,13 @@ class TestAdapter(MemoryTestDataMixin, unittest.TestCase):
|
|||
mem_depth=len(data["expected"]), separate_rw=False)
|
||||
self.converter_readback_test(dut, data["pattern"], data["expected"])
|
||||
|
||||
def test_up_converter_writes_not_sequential(self):
|
||||
# Verify that not sequential writes to single DRAM word creates same result as sequential one
|
||||
data = self.pattern_test_data["8bit_to_32bit_not_sequential"]
|
||||
dut = ConverterDUT(user_data_width=8, native_data_width=32,
|
||||
mem_depth=len(data["expected"]), separate_rw=False)
|
||||
self.converter_readback_test(dut, data["pattern"], data["expected"])
|
||||
|
||||
def cdc_readback_test(self, dut, pattern, mem_expected, clocks):
|
||||
assert len(set(adr for adr, _ in pattern)) == len(pattern), "Pattern has duplicates!"
|
||||
read_data = []
|
||||
|
|
Loading…
Reference in New Issue