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bankmachine: rename fifo to cmd_buffer and allow depth < 2 (will be used to reduce logic when performance is not the priority)

This commit is contained in:
Florent Kermarrec 2016-05-02 20:50:55 +02:00
parent 8d29e5a905
commit 7ce42d5324
5 changed files with 36 additions and 34 deletions
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8
litedram/common.py
View File

@ -59,11 +59,11 @@ def data_layout(dw):
class InternalInterface(Record):
def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
def __init__(self, aw, dw, nbanks, cmd_buffer_depth, read_latency, write_latency):
self.aw = aw
self.dw = dw
self.nbanks = nbanks
self.req_queue_size = req_queue_size
self.cmd_buffer_depth = cmd_buffer_depth
self.read_latency = read_latency
self.write_latency = write_latency
@ -73,10 +73,10 @@ class InternalInterface(Record):
class UserInterface(Record):
def __init__(self, aw, dw, req_queue_size, read_latency, write_latency):
def __init__(self, aw, dw, cmd_buffer_depth, read_latency, write_latency):
self.aw = aw
self.dw = dw
self.req_queue_size = req_queue_size
self.cmd_buffer_depth = cmd_buffer_depth
self.read_latency = read_latency
self.write_latency = write_latency

48
litedram/core/bankmachine.py
View File

@ -6,7 +6,7 @@ from litex.soc.interconnect import stream
from litedram.core.multiplexer import *
class _AddressSlicer:
class AddressSlicer:
def __init__(self, colbits, address_align):
self.colbits = colbits
self.address_align = address_align
@ -43,43 +43,45 @@ class BankMachine(Module):
# # #
# Request FIFO-
fifo = stream.SyncFIFO([("we", 1), ("adr", len(req.adr))],
controller_settings.req_queue_size)
self.submodules += fifo
# Command buffer
cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
if controller_settings.cmd_buffer_depth < 2:
cmd_buffer = stream.Buffer(cmd_buffer_layout)
else:
cmd_buffer = stream.SyncFIFO(cmd_buffer_layout,
controller_settings.cmd_buffer_depth)
self.submodules += cmd_buffer
self.comb += [
req.connect(fifo.sink, omit=["dat_w_ack", "dat_r_ack", "lock"]),
fifo.source.ready.eq(req.dat_w_ack | req.dat_r_ack),
req.lock.eq(fifo.source.valid),
req.connect(cmd_buffer.sink, omit=["dat_w_ack", "dat_r_ack", "lock"]),
cmd_buffer.source.ready.eq(req.dat_w_ack | req.dat_r_ack),
req.lock.eq(cmd_buffer.source.valid),
]
slicer = _AddressSlicer(geom_settings.colbits, address_align)
slicer = AddressSlicer(geom_settings.colbits, address_align)
# Row tracking
has_openrow = Signal()
openrow = Signal(geom_settings.rowbits)
hit = Signal()
self.comb += hit.eq(openrow == slicer.row(fifo.source.adr))
self.comb += hit.eq(openrow == slicer.row(cmd_buffer.source.adr))
track_open = Signal()
track_close = Signal()
self.sync += [
If(track_open,
has_openrow.eq(1),
openrow.eq(slicer.row(fifo.source.adr))
),
self.sync += \
If(track_close,
has_openrow.eq(0)
).Elif(track_open,
has_openrow.eq(1),
openrow.eq(slicer.row(cmd_buffer.source.adr))
)
]
# Address generation
s_row_adr = Signal()
sel_row_adr = Signal()
self.comb += [
cmd.ba.eq(n),
If(s_row_adr,
cmd.a.eq(slicer.row(fifo.source.adr))
If(sel_row_adr,
cmd.a.eq(slicer.row(cmd_buffer.source.adr))
).Else(
cmd.a.eq(slicer.col(fifo.source.adr))
cmd.a.eq(slicer.col(cmd_buffer.source.adr))
)
]
@ -95,13 +97,13 @@ class BankMachine(Module):
fsm.act("REGULAR",
If(self.refresh_req,
NextState("REFRESH")
).Elif(fifo.source.valid,
).Elif(cmd_buffer.source.valid,
If(has_openrow,
If(hit,
# Note: write-to-read specification is enforced by
# multiplexer
cmd.valid.eq(1),
If(fifo.source.we,
If(cmd_buffer.source.we,
req.dat_w_ack.eq(cmd.ready),
cmd.is_write.eq(1),
cmd.we.eq(1),
@ -132,7 +134,7 @@ class BankMachine(Module):
track_close.eq(1)
)
fsm.act("ACTIVATE",
s_row_adr.eq(1),
sel_row_adr.eq(1),
track_open.eq(1),
cmd.valid.eq(1),
cmd.is_cmd.eq(1),

6
litedram/core/controller.py
View File

@ -8,10 +8,10 @@ from litedram.core.multiplexer import *
class ControllerSettings:
def __init__(self, req_queue_size=8, read_time=32, write_time=16,
def __init__(self, cmd_buffer_depth=8, read_time=32, write_time=16,
with_bandwidth=False,
with_refresh=True):
self.req_queue_size = req_queue_size
self.cmd_buffer_depth = cmd_buffer_depth
self.read_time = read_time
self.write_time = write_time
self.with_bandwidth = with_bandwidth
@ -38,7 +38,7 @@ class LiteDRAMController(Module):
aw=geom_settings.rowbits + geom_settings.colbits - address_align,
dw=phy_settings.dfi_databits*phy_settings.nphases,
nbanks=2**geom_settings.bankbits,
req_queue_size=controller_settings.req_queue_size,
cmd_buffer_depth=controller_settings.cmd_buffer_depth,
read_latency=phy_settings.read_latency+1,
write_latency=phy_settings.write_latency+1)
self.nrowbits = geom_settings.colbits - address_align

4
litedram/frontend/crossbar.py
View File

@ -15,7 +15,7 @@ class LiteDRAMCrossbar(Module):
self.rca_bits = controller.aw
self.dw = controller.dw
self.nbanks = controller.nbanks
self.req_queue_size = controller.req_queue_size
self.cmd_buffer_depth = controller.cmd_buffer_depth
self.read_latency = controller.read_latency
self.write_latency = controller.write_latency
@ -27,7 +27,7 @@ class LiteDRAMCrossbar(Module):
if self.finalized:
raise FinalizeError
port = UserInterface(self.rca_bits + self.bank_bits,
self.dw, self.req_queue_size, self.read_latency, self.write_latency)
self.dw, self.cmd_buffer_depth, self.read_latency, self.write_latency)
self.masters.append(port)
return port

4
litedram/frontend/dma.py
View File

@ -12,7 +12,7 @@ class LiteDRAMDMAReader(Module):
# # #
if fifo_depth is None:
fifo_depth = port.req_queue_size + port.read_latency + 2
fifo_depth = port.cmd_buffer_depth + port.read_latency + 2
# request issuance
request_enable = Signal()
@ -67,7 +67,7 @@ class LiteDRAMDMAWriter(Module):
# # #
if fifo_depth is None:
fifo_depth = port.req_queue_size + port.write_latency + 2
fifo_depth = port.cmd_buffer_depth + port.write_latency + 2
fifo = SyncFIFO(port.dw, fifo_depth)
self.submodules += fifo