bench/kcu105: add a second pll to reduce frequency steps.

bench/arty.py

@@ -44,11 +44,6 @@ class _CRG(Module, AutoCSR):
         main_pll.expose_drp()
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-        sys_clk_counter = Signal(32)
-        self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
-        self.sys_clk_counter = CSRStatus(32)
-        self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
-
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~main_pll.locked)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
@@ -56,6 +51,11 @@ class _CRG(Module, AutoCSR):
         pll.create_clkout(self.cd_sys4x,        4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs,    4*sys_clk_freq, phase=90)
 
+        sys_clk_counter = Signal(32)
+        self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
+        self.sys_clk_counter = CSRStatus(32)
+        self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
+
 # Bench SoC ----------------------------------------------------------------------------------------
 
 class BenchSoC(SoCCore):

bench/common.py

@@ -86,22 +86,7 @@ class S7PLL:
         self.bus.regs.crg_main_pll_drp_write.write(1)
 
 
-class USPLL:
-    def __init__(self, bus):
-        self.bus = bus
-
-    def reset(self):
-        self.bus.regs.crg_pll_drp_reset.write(1)
-
-    def read(self, adr):
-        self.bus.regs.crg_pll_drp_adr.write(adr)
-        self.bus.regs.crg_pll_drp_read.write(1)
-        return self.bus.regs.crg_pll_drp_dat_r.read()
-
-    def write(self, adr, value):
-        self.bus.regs.crg_pll_drp_adr.write(adr)
-        self.bus.regs.crg_pll_drp_dat_w.write(value)
-        self.bus.regs.crg_pll_drp_write.write(1)
+class USPLL(S7PLL): pass
 
 # Bench Controller ---------------------------------------------------------------------------------
 
@@ -186,7 +171,7 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
 
 # Bench Test ---------------------------------------------------------------------------------------
 
-def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=10):
+def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=40):
     import time
     from litex import RemoteClient
 
@@ -213,13 +198,13 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
     tested_vco_divs = []
     for clk_freq in range(int(freq_min), int(freq_max), int(freq_step)):
         # Compute VCO divider, skip if already tested.
-        vco_div = int(vco_freq/(4*clk_freq))
+        vco_div = int(vco_freq/clk_freq)
         if vco_div in tested_vco_divs:
             continue
         tested_vco_divs.append(vco_div)
 
         print("-"*40)
-        print("sys_clk = {}MHz...".format(vco_freq/4/vco_div/1e6))
+        print("sys_clk = {}MHz...".format(vco_freq/vco_div/1e6))
         print("-"*40)
 
         # Reconfigure PLL to change sys_clk

bench/genesys2.py

@@ -43,17 +43,17 @@ class _CRG(Module, AutoCSR):
         main_pll.expose_drp()
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-        sys_clk_counter = Signal(32)
-        self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
-        self.sys_clk_counter = CSRStatus(32)
-        self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
-
         self.submodules.pll = pll = S7PLL(speedgrade=-2)
         self.comb += pll.reset.eq(~main_pll.locked)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
 
+        sys_clk_counter = Signal(32)
+        self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
+        self.sys_clk_counter = CSRStatus(32)
+        self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
+
 # Bench SoC ----------------------------------------------------------------------------------------
 
 class BenchSoC(SoCCore):

bench/kc705.py

@@ -43,17 +43,17 @@ class _CRG(Module, AutoCSR):
         main_pll.expose_drp()
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-        sys_clk_counter = Signal(32)
-        self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
-        self.sys_clk_counter = CSRStatus(32)
-        self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
-
         self.submodules.pll = pll = S7PLL(speedgrade=-2)
         self.comb += pll.reset.eq(~main_pll.locked)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
 
+        sys_clk_counter = Signal(32)
+        self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
+        self.sys_clk_counter = CSRStatus(32)
+        self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
+
 # Bench SoC ----------------------------------------------------------------------------------------
 
 class BenchSoC(SoCCore):

bench/kcu105.py

@@ -26,21 +26,27 @@ from litedram.phy import usddrphy
 
 class _CRG(Module, AutoCSR):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys    = ClockDomain()
-        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
-        self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200 = ClockDomain()
-        self.clock_domains.cd_uart   = ClockDomain()
+        self.clock_domains.cd_sys_pll = ClockDomain()
+        self.clock_domains.cd_sys     = ClockDomain()
+        self.clock_domains.cd_sys4x   = ClockDomain(reset_less=True)
+        self.clock_domains.cd_pll4x   = ClockDomain(reset_less=True)
+        self.clock_domains.cd_clk200  = ClockDomain()
+        self.clock_domains.cd_uart    = ClockDomain()
 
         # # #
 
+        self.submodules.main_pll = main_pll = USMMCM(speedgrade=-2)
+        self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
+        main_pll.register_clkin(platform.request("clk125"), 125e6)
+        main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
+        main_pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
+        main_pll.create_clkout(self.cd_uart,   100e6)
+        main_pll.expose_drp()
+
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
-        pll.register_clkin(platform.request("clk125"), 125e6)
+        self.comb += pll.reset.eq(~main_pll.locked)
+        pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_pll4x,  sys_clk_freq*4, buf=None, with_reset=False)
-        pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
-        pll.create_clkout(self.cd_uart,   100e6)
-        pll.expose_drp()
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
@@ -117,7 +123,7 @@ def main():
     if args.test:
         from common import us_bench_test
         us_bench_test(
-            freq_min      = 60e6,
+            freq_min      = 80e6,
             freq_max      = 180e6,
             freq_step     = 1e6,
             vco_freq      = soc.crg.pll.compute_config()["vco"],