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Merge pull request #352 from maribu/litedram/phy/lpddrX/commands.py/fix-invalid-escape-sequence 

litedram/phy/lpddr*: fix use of invalid escape sequence
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enjoy-digital 2024-03-25 19:06:08 +01:00 committed by GitHub
parent d6bf98790f 37e1f346e5
commit 7dacfaf684
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2 changed files with 32 additions and 32 deletions
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10
litedram/phy/lpddr4/commands.py
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@ -206,11 +206,11 @@ class Command(Module):
"BL": lambda: 0, # on-the-fly burst length, not using
"AP": lambda: self.dfi.address[10], # auto precharge
"AB": lambda: self.dfi.address[10], # all banks
"BA(\d+)": lambda i: self.dfi.bank[i],
"R(\d+)": lambda i: self.dfi.address[i], # row
"C(\d+)": lambda i: self.dfi.address[i], # column
"MA(\d+)": lambda i: mr_address[i], # mode register address
"OP(\d+)": lambda i: self.dfi.address[i], # mode register value, or operand for MPC
"BA(\\d+)": lambda i: self.dfi.bank[i],
"R(\\d+)": lambda i: self.dfi.address[i], # row
"C(\\d+)": lambda i: self.dfi.address[i], # column
"MA(\\d+)": lambda i: mr_address[i], # mode register address
"OP(\\d+)": lambda i: self.dfi.address[i], # mode register value, or operand for MPC
}
for pattern, value in rules.items():
m = re.match(pattern, bit)

14
litedram/phy/lpddr5/commands.py
View File

@ -282,20 +282,20 @@ class Command(Module):
"AB": lambda: self.dfi.address[10], # all banks
"AP": lambda: self.dfi.address[10], # auto precharge
"RFM": lambda: 0, # TODO: 1=RFM, 0=REF (Refresh Managemenent, only if r/o MR[27][0]=1, else always REF)
"SB(\d+)": lambda i: 0, # sub-bank selection related to RFM
"SB(\\d+)": lambda i: 0, # sub-bank selection related to RFM
"WS_WR": lambda: self.wck_sync == WCKSyncType.WR, # Write WCK2CK SYNC
"WS_RD": lambda: self.wck_sync == WCKSyncType.RD, # Read WCK2CK SYNC
"WS_FS": lambda: self.wck_sync == WCKSyncType.FS, # FAST SYNC
"DC(\d+)": lambda i: 0, # Data Copy, unimplemented
"DC(\\d+)": lambda i: 0, # Data Copy, unimplemented
"WRX": lambda: 0, # Write X function, unimplemented
"WXSA": lambda: 0, # Write X function, unimplemented
"WXSB": lambda: 0, # Write X function, unimplemented
"BA(\d+)": lambda i: self.dfi.bank[i], # only BA0-2 is used, in BG/B16 modes we always refresh banks (x, x+8)
"R(\d+)": lambda i: self.dfi.address[i], # row
"BA(\\d+)": lambda i: self.dfi.bank[i], # only BA0-2 is used, in BG/B16 modes we always refresh banks (x, x+8)
"R(\\d+)": lambda i: self.dfi.address[i], # row
# LPDDR5 specs split the regular column address into C[5:0] "column address" and B[3:0] "burst address"
"C(\d+)": lambda i: self.dfi.address[i + 4],
"MA(\d+)": lambda i: mr_address[i], # mode register address
"OP(\d+)": lambda i: op[i], # mode register value, or operand for MPC
"C(\\d+)": lambda i: self.dfi.address[i + 4],
"MA(\\d+)": lambda i: mr_address[i], # mode register address
"OP(\\d+)": lambda i: op[i], # mode register value, or operand for MPC
}
for pattern, value in rules.items():