test/test_bist: remove vcd generation (only useful for debug)
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@ -75,7 +75,7 @@ class TestBIST(unittest.TestCase):
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# simulation
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generators = [main_generator(dut)]
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run_simulation(dut, main_generator(dut), vcd_name="generator.vcd")
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run_simulation(dut, main_generator(dut))
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self.assertEqual(self.errors, 0)
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def test_bist(self):
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@ -123,4 +123,4 @@ class TestBIST(unittest.TestCase):
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mem.write_handler(dut.write_port),
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mem.read_handler(dut.read_port)
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]
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run_simulation(dut, generators, vcd_name="bist.vcd")
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run_simulation(dut, generators)
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