Merge pull request #84 from open-design/is42s16320

modules: SDRAM: add IS42S16320 support
2019-06-02 18:38:12 +02:00 · 2019-06-02 18:38:12 +02:00 · 7fbe0b712c
parent 8e2df17747 5c66547334
commit 7fbe0b712c
1 changed files with 11 additions and 0 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -103,6 +103,17 @@ class IS42S16160(SDRAMModule):
    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)}


+class IS42S16320(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)}
+
+
 class MT48LC4M16(SDRAMModule):
    memtype = "SDR"
    # geometry