Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #84 from open-design/is42s16320 

modules: SDRAM: add IS42S16320 support
This commit is contained in:
enjoy-digital 2019-06-02 18:38:12 +02:00 committed by GitHub
parent 8e2df17747 5c66547334
commit 7fbe0b712c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
litedram/modules.py
View File

@ -103,6 +103,17 @@ class IS42S16160(SDRAMModule):
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)}
class IS42S16320(SDRAMModule):
memtype = "SDR"
# geometry
nbanks = 4
nrows = 8192
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)}
class MT48LC4M16(SDRAMModule): class MT48LC4M16(SDRAMModule):
memtype = "SDR" memtype = "SDR"
# geometry # geometry