phy/ecp5ddrphy: reintegrate old BitSlip (issue with new one on ECP5).

This commit is contained in:
Florent Kermarrec 2020-10-12 19:40:00 +02:00
parent 1ee4fa25c4
commit 80b5ed30e9
1 changed files with 24 additions and 0 deletions

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@ -24,6 +24,30 @@ from litex.soc.interconnect.csr import *
from litedram.common import *
from litedram.phy.dfi import *
# BitSlip ------------------------------------------------------------------------------------------
# FIXME: Use BitSlip from litedram.common.
class BitSlip(Module):
def __init__(self, dw, rst=None, slp=None, cycles=1):
self.i = Signal(dw)
self.o = Signal(dw)
self.rst = Signal() if rst is None else rst
self.slp = Signal() if slp is None else slp
# # #
value = Signal(max=cycles*dw)
self.sync += If(self.slp, value.eq(value + 1))
self.sync += If(self.rst, value.eq(0))
r = Signal((cycles+1)*dw, reset_less=True)
self.sync += r.eq(Cat(r[dw:], self.i))
cases = {}
for i in range(cycles*dw):
cases[i] = self.o.eq(r[i:dw+i])
self.comb += Case(value, cases)
# Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
class ECP5DDRPHYInit(Module):