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phy/s7ddrphy: also add bitslip on dqs.

This commit is contained in:
Florent Kermarrec 2020-10-08 18:17:47 +02:00
parent 0ac23fde52
commit 83d70a3eb9
1 changed files with 6 additions and 5 deletions
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11
litedram/phy/s7ddrphy.py
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@ -212,8 +212,9 @@ class S7DDRPHY(Module, AutoCSR):
postamble = dqs_postamble, postamble = dqs_postamble,
wlevel_en = self._wlevel_en.storage, wlevel_en = self._wlevel_en.storage,
wlevel_strobe = self._wlevel_strobe.re, wlevel_strobe = self._wlevel_strobe.re,
register = not with_odelay) register = False) # FIXME: fix not with_odelay case.
self.submodules += dqs_oe_delay, dqs_pattern dqs_bitslip = BitSlip(8, i=dqs_pattern.o, cycles=1)
self.submodules += dqs_oe_delay, dqs_pattern, dqs_bitslip
self.comb += dqs_oe_delay.input.eq(dqs_preamble | dqs_oe | dqs_postamble) self.comb += dqs_oe_delay.input.eq(dqs_preamble | dqs_oe | dqs_postamble)
for i in range(databits//8): for i in range(databits//8):
dqs_o_no_delay = Signal() dqs_o_no_delay = Signal()
@ -228,7 +229,7 @@ class S7DDRPHY(Module, AutoCSR):
i_RST = ResetSignal() | self._rst.storage, i_RST = ResetSignal() | self._rst.storage,
i_CLK = ClockSignal(ddr_clk) if with_odelay else ClockSignal(ddr_clk+"_dqs"), i_CLK = ClockSignal(ddr_clk) if with_odelay else ClockSignal(ddr_clk+"_dqs"),
i_CLKDIV = ClockSignal(), i_CLKDIV = ClockSignal(),
**{f"i_D{n+1}": dqs_pattern.o[n] for n in range(8)}, **{f"i_D{n+1}": dqs_bitslip.o[n] for n in range(8)},
i_OCE = 1, i_OCE = 1,
o_OFB = dqs_o_no_delay if with_odelay else Signal(), o_OFB = dqs_o_no_delay if with_odelay else Signal(),
o_OQ = Signal() if with_odelay else dqs_o_no_delay, o_OQ = Signal() if with_odelay else dqs_o_no_delay,
@ -264,7 +265,7 @@ class S7DDRPHY(Module, AutoCSR):
# DM --------------------------------------------------------------------------------------- # DM ---------------------------------------------------------------------------------------
for i in range(databits//8): for i in range(databits//8):
dm_o_nodelay = Signal() dm_o_nodelay = Signal()
dm_o_bitslip = BitSlip(8, dm_o_bitslip = BitSlip(8,
i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]), i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]),
cycles = 1) cycles = 1)
self.submodules += dm_o_bitslip self.submodules += dm_o_bitslip
@ -312,7 +313,7 @@ class S7DDRPHY(Module, AutoCSR):
dq_i_delayed = Signal() dq_i_delayed = Signal()
dq_t = Signal() dq_t = Signal()
dq_i_data = Signal(8) dq_i_data = Signal(8)
dq_o_bitslip = BitSlip(8, dq_o_bitslip = BitSlip(8,
i = Cat(*[dfi.phases[n//2].wrdata[n%2*databits+i] for n in range(8)]), i = Cat(*[dfi.phases[n//2].wrdata[n%2*databits+i] for n in range(8)]),
cycles = 1) cycles = 1)
self.submodules += dq_o_bitslip self.submodules += dq_o_bitslip