frontend/adaptation: refactor up-converter logic to use FSM for clarity
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Jędrzej Boczar
parent
efe9a44c93
commit
84fb7d338a
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@ -175,6 +175,33 @@ class LiteDRAMNativePortUpConverter(Module):
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read_lock = Signal()
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rw_collision = Signal()
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self.submodules.fsm = fsm = FSM()
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fsm.act("NEW",
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# when the first command is received, send it immediatelly
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If(port_from.cmd.valid & ~read_lock,
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port_to.cmd.valid.eq(1),
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port_to.cmd.we.eq(port_from.cmd.we),
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port_to.cmd.addr.eq(port_from.cmd.addr[log2_int(ratio):]),
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port_from.cmd.ready.eq(port_to.cmd.ready),
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If(port_from.cmd.ready,
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NextState("FILL"),
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)
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),
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)
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fsm.act("FILL",
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If(next_cmd, # send current command info when we have to go to the next command
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cmd_buffer.sink.valid.eq(1),
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cmd_buffer.sink.sel.eq(sel),
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cmd_buffer.sink.we.eq(cmd_we),
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If(cmd_buffer.sink.ready,
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NextValue(sel, 0),
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NextState("NEW"),
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)
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).Else( # acknowledge incomming commands, while filling `sel`
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port_from.cmd.ready.eq(port_from.cmd.valid),
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)
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)
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self.comb += [
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cmd_buffer.source.ready.eq(wdata_finished | rdata_finished),
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addr_changed.eq(cmd_addr[log2_int(ratio):] != port_from.cmd.addr[log2_int(ratio):]),
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@ -186,39 +213,15 @@ class LiteDRAMNativePortUpConverter(Module):
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# * we received all the `ratio` commands
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# * this is the last command in a sequence
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next_cmd.eq(addr_changed | (cmd_we != port_from.cmd.we) | (sel == 2**ratio - 1) | cmd_last),
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If(sel == 0,
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# when the first command is received, send it immediatelly
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If(port_from.cmd.valid & ~read_lock,
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port_to.cmd.valid.eq(1),
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port_to.cmd.we.eq(port_from.cmd.we),
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port_to.cmd.addr.eq(port_from.cmd.addr[log2_int(ratio):]),
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port_from.cmd.ready.eq(port_to.cmd.ready),
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)
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).Else(
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# we have already sent the initial command, now either continue sending cmd.ready
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# to the master or send the current command if we have to go to next one faster
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If(next_cmd,
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cmd_buffer.sink.valid.eq(1),
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cmd_buffer.sink.sel.eq(sel),
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cmd_buffer.sink.we.eq(cmd_we),
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).Else(
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port_from.cmd.ready.eq(port_from.cmd.valid),
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)
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),
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]
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self.sync += [
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# whenever a command gets accepted, store it and update `sel` based on address
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If(port_from.cmd.valid & port_from.cmd.ready,
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cmd_addr.eq(port_from.cmd.addr),
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cmd_we.eq(port_from.cmd.we),
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cmd_last.eq(port_from.cmd.last),
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sel.eq(sel | (1 << port_from.cmd.addr[:log2_int(ratio)])),
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),
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# clear `sel` after the command has been sent for data procesing
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If(cmd_buffer.sink.valid & cmd_buffer.sink.ready,
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sel.eq(0),
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),
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# block sending read command if we have just written to that address
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If(wdata_finished,
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read_lock.eq(0),
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@ -271,11 +274,12 @@ class LiteDRAMNativePortUpConverter(Module):
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if mode == "write" or mode == "both":
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# queue write data not to miss it when the lower chunks haven't been reqested
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wdata_fifo = stream.SyncFIFO(port_from.wdata.description, ratio - 1)
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wdata_buffer = stream.SyncFIFO(port_to.wdata.description, 0)
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wdata_converter = stream.StrideConverter(
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port_from.wdata.description,
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port_to.wdata.description,
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reverse=reverse)
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self.submodules += wdata_converter, wdata_fifo
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self.submodules += wdata_converter, wdata_fifo, wdata_buffer
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# shift register with a bitmask of current chunk
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wdata_chunk = Signal(ratio, reset=1)
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@ -299,6 +303,7 @@ class LiteDRAMNativePortUpConverter(Module):
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self.comb += [
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# port_from -> wdata_fifo -> wdata_converter
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port_from.wdata.connect(wdata_fifo.sink),
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wdata_buffer.source.connect(port_to.wdata),
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wdata_chunk_valid.eq((cmd_buffer.source.sel & wdata_chunk) != 0),
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If(cmd_buffer.source.valid & cmd_buffer.source.we,
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# when the current chunk is valid, read it from wdata_fifo
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@ -311,10 +316,10 @@ class LiteDRAMNativePortUpConverter(Module):
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wdata_converter.sink.valid.eq(1),
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),
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),
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port_to.wdata.valid.eq(wdata_converter.source.valid),
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port_to.wdata.data.eq(wdata_converter.source.data),
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port_to.wdata.we.eq(wdata_converter.source.we & wdata_sel),
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wdata_converter.source.ready.eq(port_to.wdata.ready),
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wdata_buffer.sink.valid.eq(wdata_converter.source.valid),
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wdata_buffer.sink.data.eq(wdata_converter.source.data),
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wdata_buffer.sink.we.eq(wdata_converter.source.we & wdata_sel),
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wdata_converter.source.ready.eq(wdata_buffer.sink.ready),
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wdata_finished.eq(wdata_converter.sink.valid & wdata_converter.sink.ready
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& wdata_chunk[ratio-1]),
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]
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@ -327,6 +332,10 @@ class LiteDRAMNativePortConverter(Module):
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assert port_from.mode == port_to.mode
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# # #
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print('#' * 80)
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print('LiteDRAMNativePortConverter')
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print('port_from.data_width', end=' = '); __import__('pprint').pprint(port_from.data_width)
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print('port_to.data_width ', end=' = '); __import__('pprint').pprint(port_to.data_width)
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mode = port_from.mode
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