drive odt of all ranks, fixes and test non regression with 1 rank

examples/litedram_gen.py

@@ -72,7 +72,8 @@ def get_dram_ios(core_config):
             Subsignal("clk_p", Pins("X")),
             Subsignal("clk_n", Pins("X")),
             Subsignal("cke", Pins("X")),
-            Subsignal("odt", Pins("X")),
+            Subsignal("odt", Pins(
+                "X "*core_config["sdram_rank_nb"])),
             Subsignal("reset_n", Pins("X"))
         ),
     ]

litedram/common.py

@@ -82,7 +82,6 @@ class LiteDRAMInterface(Record):
     def __init__(self, address_align, settings):
         rankbits = log2_int(settings.phy.nranks)
         self.address_width = settings.geom.rowbits + settings.geom.colbits + rankbits - address_align
-        print(self.address_width)
         self.data_width = settings.phy.dfi_databits*settings.phy.nphases
         self.nbanks = settings.phy.nranks*(2**settings.geom.bankbits)
         self.nranks = settings.phy.nranks

litedram/core/multiplexer.py

@@ -95,13 +95,13 @@ class _Steerer(Module):
 
         for phase, sel in zip(dfi.phases, self.sel):
             self.comb += phase.cke.eq(1)
-            if hasattr(phase, "odt"):
-                self.comb += phase.odt.eq(1) # FIXME: constant for multi-rank?
             if hasattr(phase, "reset_n"):
                 self.comb += phase.reset_n.eq(1)
 
             nranks = len(phase.cs_n)
             rankbits = log2_int(nranks)
+            if hasattr(phase, "odt"):
+                self.comb += phase.odt.eq(2**rankbits - 1) # FIXME: dynamic drive for multi-rank
             if rankbits:
                 rank_decoder = Decoder(rankbits)
                 self.submodules += rank_decoder

litedram/dfii.py

@@ -40,8 +40,8 @@ class PhaseInjector(Module, AutoCSR):
 class DFIInjector(Module, AutoCSR):
     def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
         inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
-        self.slave = dfi.Interface(addressbits, nranks, bankbits, databits, nphases)
-        self.master = dfi.Interface(addressbits, nranks, bankbits, databits, nphases)
+        self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
         self._control = CSRStorage(4)  # sel, cke, odt, reset_n
 

litedram/phy/s7ddrphy.py

@@ -170,7 +170,7 @@ class S7DDRPHY(Module, AutoCSR):
                         p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
                         p_SERDES_MODE="MASTER",
 
-                        o_OQ=pads.ba[i],
+                        o_OQ=pads.cs_n[i],
                         i_OCE=1,
                         i_RST=ResetSignal(),
                         i_CLK=ClockSignal(ddr_clk), i_CLKDIV=ClockSignal(),