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Account for CWL in write to read timing

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2018-09-29 12:39:40 -04:00
parent 5fb8afe7e5
commit 8f14211f00
1 changed files with 3 additions and 2 deletions
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5
litedram/core/multiplexer.py
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@ -10,7 +10,7 @@ from litex.soc.interconnect.csr import AutoCSR
from litedram.common import * from litedram.common import *
from litedram.core.perf import Bandwidth from litedram.core.perf import Bandwidth
import math
class _CommandChooser(Module): class _CommandChooser(Module):
def __init__(self, requests): def __init__(self, requests):
@ -229,8 +229,9 @@ class Multiplexer(Module, AutoCSR):
self.comb += cas_allowed.eq(tccdcon.ready) self.comb += cas_allowed.eq(tccdcon.ready)
# tWTR timing (Write to Read delay) # tWTR timing (Write to Read delay)
write_latency = math.ceil(settings.phy.cwl / settings.phy.nphases)
self.submodules.twtrcon = twtrcon = tXXDController( self.submodules.twtrcon = twtrcon = tXXDController(
settings.timing.tWTR + settings.timing.tWTR + write_latency +
# tCCD must be added since tWTR begins after the transfer is complete # tCCD must be added since tWTR begins after the transfer is complete
settings.timing.tCCD if settings.timing.tCCD is not None else 0) settings.timing.tCCD if settings.timing.tCCD is not None else 0)
self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write()) self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write())