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phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally.

This commit is contained in:
Florent Kermarrec 2020-06-29 16:09:14 +02:00
parent fa7d91a053
commit 9044c10408
1 changed files with 18 additions and 17 deletions
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35
litedram/phy/ecp5ddrphy.py
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@ -21,10 +21,11 @@ from litedram.phy.dfi import *
# Lattice ECP5 DDR PHY Initialization -------------------------------------------------------------- # Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
class ECP5DDRPHYInit(Module): class ECP5DDRPHYInit(Module):
def __init__(self, eclk_cd): def __init__(self):
self.pause = Signal() self.pause = Signal()
self.stop = Signal() self.stop = Signal()
self.delay = Signal() self.delay = Signal()
self.reset = Signal()
# # # # # #
@ -40,7 +41,7 @@ class ECP5DDRPHYInit(Module):
delay = Signal() delay = Signal()
self.specials += Instance("DDRDLLA", self.specials += Instance("DDRDLLA",
i_CLK = ClockSignal("sys2x"), i_CLK = ClockSignal("sys2x"),
i_RST = ResetSignal(), i_RST = ResetSignal("init"),
i_UDDCNTLN = ~update, i_UDDCNTLN = ~update,
i_FREEZE = freeze, i_FREEZE = freeze,
o_DDRDEL = delay, o_DDRDEL = delay,
@ -48,8 +49,8 @@ class ECP5DDRPHYInit(Module):
) )
lock = Signal() lock = Signal()
lock_d = Signal() lock_d = Signal()
self.specials += MultiReg(_lock, lock) self.specials += MultiReg(_lock, lock, "init")
self.sync += lock_d.eq(lock) self.sync.init += lock_d.eq(lock)
self.comb += new_lock.eq(lock & ~lock_d) self.comb += new_lock.eq(lock & ~lock_d)
# DDRDLLA/DDQBUFM/ECLK initialization sequence --------------------------------------------- # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
@ -75,7 +76,7 @@ class ECP5DDRPHYInit(Module):
self.pause.eq(pause), self.pause.eq(pause),
self.stop.eq(stop), self.stop.eq(stop),
self.delay.eq(delay), self.delay.eq(delay),
ResetSignal(eclk_cd).eq(reset) self.reset.eq(reset),
] ]
# Lattice ECP5 DDR PHY ----------------------------------------------------------------------------- # Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
@ -93,7 +94,7 @@ class ECP5DDRPHY(Module, AutoCSR):
assert databits%8 == 0 assert databits%8 == 0
# Init ------------------------------------------------------------------------------------- # Init -------------------------------------------------------------------------------------
self.submodules.init = ClockDomainsRenamer("init")(ECP5DDRPHYInit("sys2x")) self.submodules.init = ECP5DDRPHYInit()
# Parameters ------------------------------------------------------------------------------- # Parameters -------------------------------------------------------------------------------
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
@ -149,7 +150,7 @@ class ECP5DDRPHY(Module, AutoCSR):
for i in range(len(pads.clk_p)): for i in range(len(pads.clk_p)):
sd_clk_se = Signal() sd_clk_se = Signal()
self.specials += Instance("ODDRX2F", self.specials += Instance("ODDRX2F",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_D0 = 0, i_D0 = 0,
@ -162,7 +163,7 @@ class ECP5DDRPHY(Module, AutoCSR):
# Addresses and Commands --------------------------------------------------------------- # Addresses and Commands ---------------------------------------------------------------
for i in range(addressbits): for i in range(addressbits):
self.specials += Instance("ODDRX2F", self.specials += Instance("ODDRX2F",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_D0 = dfi.phases[0].address[i], i_D0 = dfi.phases[0].address[i],
@ -173,7 +174,7 @@ class ECP5DDRPHY(Module, AutoCSR):
) )
for i in range(bankbits): for i in range(bankbits):
self.specials += Instance("ODDRX2F", self.specials += Instance("ODDRX2F",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_D0 = dfi.phases[0].bank[i], i_D0 = dfi.phases[0].bank[i],
@ -190,7 +191,7 @@ class ECP5DDRPHY(Module, AutoCSR):
for name in controls: for name in controls:
for i in range(len(getattr(pads, name))): for i in range(len(getattr(pads, name))):
self.specials += Instance("ODDRX2F", self.specials += Instance("ODDRX2F",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_D0 = getattr(dfi.phases[0], name)[i], i_D0 = getattr(dfi.phases[0], name)[i],
@ -233,7 +234,7 @@ class ECP5DDRPHY(Module, AutoCSR):
# Clocks / Reset # Clocks / Reset
i_SCLK = ClockSignal("sys"), i_SCLK = ClockSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_DDRDEL = self.init.delay, i_DDRDEL = self.init.delay,
i_PAUSE = self.init.pause | self._dly_sel.storage[i], i_PAUSE = self.init.pause | self._dly_sel.storage[i],
@ -295,7 +296,7 @@ class ECP5DDRPHY(Module, AutoCSR):
dm_bl8_cases[1] = dm_o_data_muxed.eq(dm_o_data_d[4:]) dm_bl8_cases[1] = dm_o_data_muxed.eq(dm_o_data_d[4:])
self.sync += Case(bl8_chunk, dm_bl8_cases) self.sync += Case(bl8_chunk, dm_bl8_cases)
self.specials += Instance("ODDRX2DQA", self.specials += Instance("ODDRX2DQA",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_DQSW270 = dqsw270, i_DQSW270 = dqsw270,
@ -310,7 +311,7 @@ class ECP5DDRPHY(Module, AutoCSR):
dqs_oe_n = Signal() dqs_oe_n = Signal()
self.specials += [ self.specials += [
Instance("ODDRX2DQSB", Instance("ODDRX2DQSB",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_DQSW = dqsw, i_DQSW = dqsw,
@ -321,7 +322,7 @@ class ECP5DDRPHY(Module, AutoCSR):
o_Q = dqs o_Q = dqs
), ),
Instance("TSHX2DQSA", Instance("TSHX2DQSA",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_DQSW = dqsw, i_DQSW = dqsw,
@ -359,7 +360,7 @@ class ECP5DDRPHY(Module, AutoCSR):
self.sync += Case(bl8_chunk, dq_bl8_cases) self.sync += Case(bl8_chunk, dq_bl8_cases)
self.specials += [ self.specials += [
Instance("ODDRX2DQA", Instance("ODDRX2DQA",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_DQSW270 = dqsw270, i_DQSW270 = dqsw270,
@ -378,7 +379,7 @@ class ECP5DDRPHY(Module, AutoCSR):
o_Z = dq_i_delayed o_Z = dq_i_delayed
), ),
Instance("IDDRX2DQA", Instance("IDDRX2DQA",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_DQSR90 = dqsr90, i_DQSR90 = dqsr90,
@ -415,7 +416,7 @@ class ECP5DDRPHY(Module, AutoCSR):
] ]
self.specials += [ self.specials += [
Instance("TSHX2DQA", Instance("TSHX2DQA",
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_DQSW270 = dqsw270, i_DQSW270 = dqsw270,