phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally.
This commit is contained in:
Florent Kermarrec
parent
fa7d91a053
commit
9044c10408
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@ -21,10 +21,11 @@ from litedram.phy.dfi import *
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# Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
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class ECP5DDRPHYInit(Module):
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def __init__(self, eclk_cd):
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def __init__(self):
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self.pause = Signal()
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self.stop = Signal()
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self.delay = Signal()
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self.reset = Signal()
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# # #
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@ -40,7 +41,7 @@ class ECP5DDRPHYInit(Module):
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delay = Signal()
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self.specials += Instance("DDRDLLA",
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i_CLK = ClockSignal("sys2x"),
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i_RST = ResetSignal(),
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i_RST = ResetSignal("init"),
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i_UDDCNTLN = ~update,
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i_FREEZE = freeze,
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o_DDRDEL = delay,
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@ -48,8 +49,8 @@ class ECP5DDRPHYInit(Module):
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)
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lock = Signal()
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lock_d = Signal()
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self.specials += MultiReg(_lock, lock)
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self.sync += lock_d.eq(lock)
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self.specials += MultiReg(_lock, lock, "init")
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self.sync.init += lock_d.eq(lock)
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self.comb += new_lock.eq(lock & ~lock_d)
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# DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
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@ -75,7 +76,7 @@ class ECP5DDRPHYInit(Module):
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self.pause.eq(pause),
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self.stop.eq(stop),
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self.delay.eq(delay),
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ResetSignal(eclk_cd).eq(reset)
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self.reset.eq(reset),
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]
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# Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
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@ -93,7 +94,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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assert databits%8 == 0
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# Init -------------------------------------------------------------------------------------
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self.submodules.init = ClockDomainsRenamer("init")(ECP5DDRPHYInit("sys2x"))
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self.submodules.init = ECP5DDRPHYInit()
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# Parameters -------------------------------------------------------------------------------
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cl, cwl = get_cl_cw(memtype, tck)
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@ -149,7 +150,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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for i in range(len(pads.clk_p)):
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sd_clk_se = Signal()
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = 0,
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@ -162,7 +163,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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# Addresses and Commands ---------------------------------------------------------------
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for i in range(addressbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = dfi.phases[0].address[i],
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@ -173,7 +174,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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)
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for i in range(bankbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = dfi.phases[0].bank[i],
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@ -190,7 +191,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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for name in controls:
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for i in range(len(getattr(pads, name))):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = getattr(dfi.phases[0], name)[i],
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@ -233,7 +234,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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# Clocks / Reset
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_DDRDEL = self.init.delay,
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i_PAUSE = self.init.pause | self._dly_sel.storage[i],
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@ -295,7 +296,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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dm_bl8_cases[1] = dm_o_data_muxed.eq(dm_o_data_d[4:])
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self.sync += Case(bl8_chunk, dm_bl8_cases)
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self.specials += Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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@ -310,7 +311,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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dqs_oe_n = Signal()
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self.specials += [
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Instance("ODDRX2DQSB",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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@ -321,7 +322,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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o_Q = dqs
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),
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Instance("TSHX2DQSA",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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@ -359,7 +360,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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self.sync += Case(bl8_chunk, dq_bl8_cases)
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self.specials += [
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Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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@ -378,7 +379,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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o_Z = dq_i_delayed
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),
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Instance("IDDRX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSR90 = dqsr90,
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@ -415,7 +416,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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]
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self.specials += [
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Instance("TSHX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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