test/test_wishbone: add comments/cleanup.

test/test_wishbone.py

@@ -26,7 +26,9 @@ class TestWishbone(MemoryTestDataMixin, unittest.TestCase):
             def __init__(self):
                 self.port = port
                 self.wb   = wishbone
-                self.submodules += LiteDRAMWishbone2Native(self.wb, self.port,
+                self.submodules += LiteDRAMWishbone2Native(
+                    wishbone     = self.wb,
+                    port         = self.port,
                     base_address = base_address)
                 self.mem = DRAMMemory(port.data_width, len(mem_expected))
 
@@ -46,59 +48,64 @@ class TestWishbone(MemoryTestDataMixin, unittest.TestCase):
         self.assertEqual(dut.mem.mem, mem_expected)
 
     def test_wishbone_8bit(self):
+        # Verify Wishbone with 8-bit data width.
         data = self.pattern_test_data["8bit"]
         wb   = wishbone.Interface(adr_width=30, data_width=8)
         port = LiteDRAMNativePort("both", address_width=30, data_width=8)
         self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
 
     def test_wishbone_32bit(self):
+        # Verify Wishbone with 32-bit data width.
         data = self.pattern_test_data["32bit"]
         wb   = wishbone.Interface(adr_width=30, data_width=32)
         port = LiteDRAMNativePort("both", address_width=30, data_width=32)
         self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
 
     def test_wishbone_64bit(self):
+        # Verify Wishbone with 64-bit data width.
         data = self.pattern_test_data["64bit"]
         wb   = wishbone.Interface(adr_width=30, data_width=64)
         port = LiteDRAMNativePort("both", address_width=30, data_width=64)
         self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
 
     def test_wishbone_64bit_to_32bit(self):
+        # Verify Wishbone with 64-bit data width down-converted to 32-bit data width.
         data = self.pattern_test_data["64bit_to_32bit"]
         wb   = wishbone.Interface(adr_width=30, data_width=64)
         port = LiteDRAMNativePort("both", address_width=30, data_width=32)
         self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
 
     def test_wishbone_32bit_to_8bit(self):
+        # Verify Wishbone with 32-bit data width down-converted to 8-bit data width.
         data = self.pattern_test_data["32bit_to_8bit"]
         wb   = wishbone.Interface(adr_width=30, data_width=32)
         port = LiteDRAMNativePort("both", address_width=30, data_width=8)
         self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
 
     def test_wishbone_32bit_base_address(self):
+        # Verify Wishbone with 32-bit data width and non-zero base address.
         data   = self.pattern_test_data["32bit"]
         wb     = wishbone.Interface(adr_width=30, data_width=32)
         port   = LiteDRAMNativePort("both", address_width=30, data_width=32)
         origin = 0x10000000
         # add offset (in data words)
         pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
-        self.wishbone_readback_test(pattern, data["expected"], wb, port,
+        self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
-            base_address=origin)
 
     def test_wishbone_64bit_to_32bit_base_address(self):
+        # Verify Wishbone with 64-bit data width down-converted to 32-bit data width and non-zero base address.
         data    = self.pattern_test_data["64bit_to_32bit"]
         wb      = wishbone.Interface(adr_width=30, data_width=64)
         port    = LiteDRAMNativePort("both", address_width=30, data_width=32)
         origin  = 0x10000000
         pattern = [(adr + origin//(64//8), data) for adr, data in data["pattern"]]
-        self.wishbone_readback_test(pattern, data["expected"], wb, port,
+        self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
-            base_address=origin)
 
     def test_wishbone_32bit_to_8bit_base_address(self):
+        # Verify Wishbone with 32-bit data width down-converted to 8-bit data width and non-zero base address.
         data    = self.pattern_test_data["32bit_to_8bit"]
         wb      = wishbone.Interface(adr_width=30, data_width=32)
         port    = LiteDRAMNativePort("both", address_width=30, data_width=8)
         origin  = 0x10000000
         pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
-        self.wishbone_readback_test(pattern, data["expected"], wb, port,
+        self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
-            base_address=origin)