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phy/model: change timing checker parameter, use a verbosity parameter

This commit is contained in:
Florent Kermarrec 2020-02-16 16:04:11 +01:00
parent 95b827d435
commit 9083822a74
1 changed files with 9 additions and 5 deletions
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14
litedram/phy/model.py
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@ -17,6 +17,11 @@ from operator import or_
import struct import struct
SDRAM_VERBOSE_OFF = 0
SDRAM_VERBOSE_STD = 1
SDRAM_VERBOSE_DBG = 2
# Bank Model --------------------------------------------------------------------------------------- # Bank Model ---------------------------------------------------------------------------------------
class BankModel(Module): class BankModel(Module):
@ -303,7 +308,7 @@ class DFITimingsChecker(Module):
curr_diff = Signal().like(ref_ps_diff) curr_diff = Signal().like(ref_ps_diff)
self.comb += curr_diff.eq(ps - (ref_ps + self.timings["tREFI"])) self.comb += curr_diff.eq(ps - (ref_ps + self.timings["tREFI"]))
# Work in 64ms periods # Work in 64ms periods
self.sync += If(ref_ps_mod < int(64e9), self.sync += If(ref_ps_mod < int(64e9),
ref_ps_mod.eq(ref_ps_mod + nphases * self.timings["tCK"])).Else(ref_ps_mod.eq(0)) ref_ps_mod.eq(ref_ps_mod + nphases * self.timings["tCK"])).Else(ref_ps_mod.eq(0))
@ -391,8 +396,7 @@ class SDRAMPHYModel(Module):
we_granularity = 8, we_granularity = 8,
init = [], init = [],
address_mapping = "ROW_BANK_COL", address_mapping = "ROW_BANK_COL",
use_timing_checker = True, verbosity = SDRAM_VERBOSE_OFF):
verbose_timing_checker = False):
# Parameters ------------------------------------------------------------------------------- # Parameters -------------------------------------------------------------------------------
burst_length = { burst_length = {
@ -434,7 +438,7 @@ class SDRAMPHYModel(Module):
self.submodules += phases self.submodules += phases
# DFI timing checker ----------------------------------------------------------------------- # DFI timing checker -----------------------------------------------------------------------
if use_timing_checker: if verbosity > SDRAM_VERBOSE_OFF:
timings = {"tCK": (1e9 / clk_freq) / nphases} timings = {"tCK": (1e9 / clk_freq) / nphases}
for name in _speedgrade_timings + _technology_timings: for name in _speedgrade_timings + _technology_timings:
@ -447,7 +451,7 @@ class SDRAMPHYModel(Module):
timings = timings, timings = timings,
refresh_mode = self.module.timing_settings.fine_refresh_mode, refresh_mode = self.module.timing_settings.fine_refresh_mode,
memtype = settings.memtype, memtype = settings.memtype,
verbose = verbose_timing_checker) verbose = verbosity > SDRAM_VERBOSE_DBG)
self.submodules += timing_checker self.submodules += timing_checker
# Bank init data --------------------------------------------------------------------------- # Bank init data ---------------------------------------------------------------------------