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phy/model: change timing checker parameter, use a verbosity parameter

This commit is contained in:
Florent Kermarrec 2020-02-16 16:04:11 +01:00
parent 95b827d435
commit 9083822a74
1 changed files with 9 additions and 5 deletions
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12
litedram/phy/model.py
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@ -17,6 +17,11 @@ from operator import or_
import struct
SDRAM_VERBOSE_OFF = 0
SDRAM_VERBOSE_STD = 1
SDRAM_VERBOSE_DBG = 2
# Bank Model ---------------------------------------------------------------------------------------
class BankModel(Module):
@ -391,8 +396,7 @@ class SDRAMPHYModel(Module):
we_granularity = 8,
init = [],
address_mapping = "ROW_BANK_COL",
use_timing_checker = True,
verbose_timing_checker = False):
verbosity = SDRAM_VERBOSE_OFF):
# Parameters -------------------------------------------------------------------------------
burst_length = {
@ -434,7 +438,7 @@ class SDRAMPHYModel(Module):
self.submodules += phases
# DFI timing checker -----------------------------------------------------------------------
if use_timing_checker:
if verbosity > SDRAM_VERBOSE_OFF:
timings = {"tCK": (1e9 / clk_freq) / nphases}
for name in _speedgrade_timings + _technology_timings:
@ -447,7 +451,7 @@ class SDRAMPHYModel(Module):
timings = timings,
refresh_mode = self.module.timing_settings.fine_refresh_mode,
memtype = settings.memtype,
verbose = verbose_timing_checker)
verbose = verbosity > SDRAM_VERBOSE_DBG)
self.submodules += timing_checker
# Bank init data ---------------------------------------------------------------------------