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phy/s7ddrphy: Only add +1 to CL for DDR3 (thanks gsomlo).

This commit is contained in:
Florent Kermarrec 2021-09-15 08:43:31 +02:00
parent 6f323f6a7a
commit 916f54e4f3
1 changed files with 4 additions and 3 deletions
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7
litedram/phy/s7ddrphy.py
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@ -37,6 +37,7 @@ class S7DDRPHY(Module, AutoCSR):
cmd_delay = None, cmd_delay = None,
ddr_clk = None, ddr_clk = None,
csr_cdc = None): csr_cdc = None):
assert memtype in ["DDR2", "DDR3"]
assert not (memtype == "DDR3" and nphases == 2) assert not (memtype == "DDR3" and nphases == 2)
phytype = self.__class__.__name__ phytype = self.__class__.__name__
pads = PHYPadsCombiner(pads) pads = PHYPadsCombiner(pads)
@ -117,9 +118,9 @@ class S7DDRPHY(Module, AutoCSR):
wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re) wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re)
# PHY settings ----------------------------------------------------------------------------- # PHY settings -----------------------------------------------------------------------------
if not with_odelay: if (memtype == "DDR3") and (not with_odelay):
# Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1 to cl # DDR3 Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1
# in MR register increases sys_clk_freq range. # to cl in MR register increases sys_clk_freq range.
cl += 1 cl += 1
self.settings = PhySettings( self.settings = PhySettings(
phytype = phytype, phytype = phytype,