Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/s7ddrphy: Only add +1 to CL for DDR3 (thanks gsomlo).

This commit is contained in:
Florent Kermarrec 2021-09-15 08:43:31 +02:00
parent 6f323f6a7a
commit 916f54e4f3
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
litedram/phy/s7ddrphy.py
View File

@ -37,6 +37,7 @@ class S7DDRPHY(Module, AutoCSR):
cmd_delay = None,
ddr_clk = None,
csr_cdc = None):
assert memtype in ["DDR2", "DDR3"]
assert not (memtype == "DDR3" and nphases == 2)
phytype = self.__class__.__name__
pads = PHYPadsCombiner(pads)
@ -117,9 +118,9 @@ class S7DDRPHY(Module, AutoCSR):
wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re)
# PHY settings -----------------------------------------------------------------------------
if not with_odelay:
# Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1 to cl
# in MR register increases sys_clk_freq range.
if (memtype == "DDR3") and (not with_odelay):
# DDR3 Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1
# to cl in MR register increases sys_clk_freq range.
cl += 1
self.settings = PhySettings(
phytype = phytype,