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test/bist_tb: adapt to new interface

This commit is contained in:
Florent Kermarrec 2016-05-23 13:27:29 +02:00
parent a016a820b5
commit 94d526a78c
1 changed files with 19 additions and 19 deletions
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38
test/bist_tb.py
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@ -29,20 +29,20 @@ class DRAMMemory:
address = 0 address = 0
pending = 0 pending = 0
while True: while True:
yield dram_port.ready.eq(0) yield dram_port.cmd.ready.eq(0)
yield dram_port.rdata_valid.eq(0) yield dram_port.rdata.valid.eq(0)
if pending: if pending:
yield dram_port.rdata_valid.eq(1) yield dram_port.rdata.valid.eq(1)
yield dram_port.rdata.eq(self.mem[address%self.depth]) yield dram_port.rdata.data.eq(self.mem[address%self.depth])
yield yield
yield dram_port.rdata_valid.eq(0) yield dram_port.rdata.valid.eq(0)
yield dram_port.rdata.eq(0) yield dram_port.rdata.data.eq(0)
pending = 0 pending = 0
elif (yield dram_port.valid): elif (yield dram_port.cmd.valid):
pending = not (yield dram_port.we) pending = not (yield dram_port.cmd.we)
address = (yield dram_port.adr) address = (yield dram_port.cmd.adr)
yield yield
yield dram_port.ready.eq(1) yield dram_port.cmd.ready.eq(1)
yield yield
@passive @passive
@ -50,20 +50,20 @@ class DRAMMemory:
address = 0 address = 0
pending = 0 pending = 0
while True: while True:
yield dram_port.ready.eq(0) yield dram_port.cmd.ready.eq(0)
yield dram_port.wdata_ready.eq(0) yield dram_port.wdata.ready.eq(0)
if pending: if pending:
yield dram_port.wdata_ready.eq(1) yield dram_port.wdata.ready.eq(1)
yield yield
self.mem[address%self.depth] = (yield dram_port.wdata) # TODO manage we self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
yield dram_port.wdata_ready.eq(0) yield dram_port.wdata.ready.eq(0)
yield yield
pending = 0 pending = 0
elif (yield dram_port.valid): elif (yield dram_port.cmd.valid):
pending = yield dram_port.we pending = yield dram_port.cmd.we
address = (yield dram_port.adr) address = (yield dram_port.cmd.adr)
yield yield
yield dram_port.ready.eq(1) yield dram_port.cmd.ready.eq(1)
yield yield