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https://github.com/enjoy-digital/litedram.git
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test: remove use of rand_wait, rename rand_level to random
This commit is contained in:
Florent Kermarrec
parent
0eef5d4d55
commit
9584c2fe88
2 changed files with 45 additions and 40 deletions
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@ -6,13 +6,6 @@ import random
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from migen import *
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def rand_wait(level):
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prng = random.Random(42)
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while prng.randrange(100) < level:
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yield
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def seed_to_data(seed, random=True, nbits=32):
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if nbits == 32:
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if random:
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@ -43,7 +36,7 @@ class DRAMMemory:
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print("0x{:08x}: 0x{:08x}".format(addr, self.mem[addr]))
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@passive
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def read_handler(self, dram_port, rdata_valid_rand_level=0):
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def read_handler(self, dram_port, rdata_valid_random=0):
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address = 0
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pending = 0
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prng = random.Random(42)
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@ -51,7 +44,8 @@ class DRAMMemory:
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while True:
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yield dram_port.rdata.valid.eq(0)
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if pending:
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yield from rand_wait(rdata_valid_rand_level)
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while prng.randrange(100) < rdata_valid_random:
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yield
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yield dram_port.rdata.valid.eq(1)
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yield dram_port.rdata.data.eq(self.mem[address%self.depth])
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yield
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@ -68,7 +62,7 @@ class DRAMMemory:
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yield
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@passive
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def write_handler(self, dram_port, wdata_ready_rand_level=0):
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def write_handler(self, dram_port, wdata_ready_random=0):
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address = 0
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pending = 0
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prng = random.Random(42)
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@ -78,7 +72,8 @@ class DRAMMemory:
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if pending:
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while (yield dram_port.wdata.valid) == 0:
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yield
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yield from rand_wait(wdata_ready_rand_level)
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while prng.randrange(100) < wdata_ready_random:
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yield
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yield dram_port.wdata.ready.eq(1)
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yield
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self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
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@ -58,25 +58,27 @@ class Read(Access):
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class TestAXI(unittest.TestCase):
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def _test_axi2native(self,
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naccesses=16, simultaneous_writes_reads=False,
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# rand_level: 0: min (no random), 100: max.
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# random: 0: min (no random), 100: max.
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# burst randomness
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id_rand_enable = False,
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len_rand_enable = False,
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data_rand_enable = False,
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# flow valid randomness
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aw_valid_rand_level = 0,
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w_valid_rand_level = 0,
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ar_valid_rand_level = 0,
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r_valid_rand_level = 0,
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aw_valid_random = 0,
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w_valid_random = 0,
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ar_valid_random = 0,
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r_valid_random = 0,
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# flow ready randomness
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w_ready_rand_level = 0,
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b_ready_rand_level = 0,
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r_ready_rand_level = 0
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w_ready_random = 0,
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b_ready_random = 0,
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r_ready_random = 0
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):
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def writes_cmd_generator(axi_port, writes):
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prng = random.Random(42)
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for write in writes:
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yield from rand_wait(aw_valid_rand_level)
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while prng.randrange(100) < aw_valid_random:
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yield
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# send command
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.addr.eq(write.addr<<2)
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@ -90,9 +92,11 @@ class TestAXI(unittest.TestCase):
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yield axi_port.aw.valid.eq(0)
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def writes_data_generator(axi_port, writes):
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prng = random.Random(42)
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for write in writes:
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for i, data in enumerate(write.data):
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yield from rand_wait(w_valid_rand_level)
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while prng.randrange(100) < w_valid_random:
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yield
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# send data
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yield axi_port.w.valid.eq(1)
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if (i == (len(write.data) - 1)):
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@ -107,6 +111,7 @@ class TestAXI(unittest.TestCase):
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axi_port.reads_enable = True
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def writes_response_generator(axi_port, writes):
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prng = random.Random(42)
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self.writes_id_errors = 0
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for write in writes:
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# wait response
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@ -114,17 +119,20 @@ class TestAXI(unittest.TestCase):
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yield
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while (yield axi_port.b.valid) == 0:
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yield
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yield from rand_wait(b_ready_rand_level)
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while prng.randrange(100) < b_ready_random:
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yield
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yield axi_port.b.ready.eq(1)
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yield
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if (yield axi_port.b.id) != write.id:
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self.writes_id_errors += 1
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def reads_cmd_generator(axi_port, reads):
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prng = random.Random(42)
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while not axi_port.reads_enable:
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yield
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for read in reads:
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yield from rand_wait(ar_valid_rand_level)
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while prng.randrange(100) < ar_valid_random:
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yield
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# send command
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.addr.eq(read.addr<<2)
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@ -138,6 +146,7 @@ class TestAXI(unittest.TestCase):
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yield axi_port.ar.valid.eq(0)
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def reads_response_data_generator(axi_port, reads):
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prng = random.Random(42)
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self.reads_data_errors = 0
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self.reads_id_errors = 0
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self.reads_last_errors = 0
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@ -150,7 +159,8 @@ class TestAXI(unittest.TestCase):
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yield
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while (yield axi_port.r.valid) == 0:
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yield
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yield from rand_wait(r_ready_rand_level)
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while prng.randrange(100) < r_ready_random:
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yield
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yield axi_port.r.ready.eq(1)
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yield
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if (yield axi_port.r.data) != data:
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@ -195,8 +205,8 @@ class TestAXI(unittest.TestCase):
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writes_response_generator(axi_port, writes),
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reads_cmd_generator(axi_port, reads),
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reads_response_data_generator(axi_port, reads),
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mem.read_handler(dram_port, rdata_valid_rand_level=r_valid_rand_level),
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mem.write_handler(dram_port, wdata_ready_rand_level=w_ready_rand_level)
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mem.read_handler(dram_port, rdata_valid_random=r_valid_random),
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mem.write_handler(dram_port, wdata_ready_random=w_ready_random)
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]
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run_simulation(dut, generators)
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#mem.show_content()
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@ -228,25 +238,25 @@ class TestAXI(unittest.TestCase):
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data_rand_enable=True)
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def test_axi2native_random_w_ready(self):
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self._test_axi2native(w_ready_rand_level=90)
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self._test_axi2native(w_ready_random=90)
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def test_axi2native_random_b_ready(self):
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self._test_axi2native(b_ready_rand_level=90)
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self._test_axi2native(b_ready_random=90)
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def test_axi2native_random_r_ready(self):
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self._test_axi2native(r_ready_rand_level=90)
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self._test_axi2native(r_ready_random=90)
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def test_axi2native_random_aw_valid(self):
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self._test_axi2native(aw_valid_rand_level=90)
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self._test_axi2native(aw_valid_random=90)
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def test_axi2native_random_w_valid(self):
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self._test_axi2native(w_valid_rand_level=90)
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self._test_axi2native(w_valid_random=90)
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def test_axi2native_random_ar_valid(self):
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self._test_axi2native(ar_valid_rand_level=90)
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self._test_axi2native(ar_valid_random=90)
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def test_axi2native_random_r_valid(self):
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self._test_axi2native(r_valid_rand_level=90)
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self._test_axi2native(r_valid_random=90)
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# now let's stress things a bit... :)
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def test_axi2native_random_all(self):
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@ -254,11 +264,11 @@ class TestAXI(unittest.TestCase):
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simultaneous_writes_reads=True,
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id_rand_enable=True,
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len_rand_enable=True,
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aw_valid_rand_level=50,
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w_ready_rand_level=50,
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b_ready_rand_level=50,
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w_valid_rand_level=50,
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ar_valid_rand_level=90,
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r_valid_rand_level=90,
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r_ready_rand_level=90
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aw_valid_random=50,
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w_ready_random=50,
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b_ready_random=50,
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w_valid_random=50,
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ar_valid_random=90,
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r_valid_random=90,
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r_ready_random=90
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)
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