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test: remove use of rand_wait, rename rand_level to random

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This commit is contained in:
Florent Kermarrec 2019-07-23 21:14:17 +02:00
parent 0eef5d4d55
commit 9584c2fe88
2 changed files with 45 additions and 40 deletions
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17
test/common.py
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@ -6,13 +6,6 @@ import random
from migen import * from migen import *
def rand_wait(level):
prng = random.Random(42)
while prng.randrange(100) < level:
yield
def seed_to_data(seed, random=True, nbits=32): def seed_to_data(seed, random=True, nbits=32):
if nbits == 32: if nbits == 32:
if random: if random:
@ -43,7 +36,7 @@ class DRAMMemory:
print("0x{:08x}: 0x{:08x}".format(addr, self.mem[addr])) print("0x{:08x}: 0x{:08x}".format(addr, self.mem[addr]))
@passive @passive
def read_handler(self, dram_port, rdata_valid_rand_level=0): def read_handler(self, dram_port, rdata_valid_random=0):
address = 0 address = 0
pending = 0 pending = 0
prng = random.Random(42) prng = random.Random(42)
@ -51,7 +44,8 @@ class DRAMMemory:
while True: while True:
yield dram_port.rdata.valid.eq(0) yield dram_port.rdata.valid.eq(0)
if pending: if pending:
yield from rand_wait(rdata_valid_rand_level) while prng.randrange(100) < rdata_valid_random:
yield
yield dram_port.rdata.valid.eq(1) yield dram_port.rdata.valid.eq(1)
yield dram_port.rdata.data.eq(self.mem[address%self.depth]) yield dram_port.rdata.data.eq(self.mem[address%self.depth])
yield yield
@ -68,7 +62,7 @@ class DRAMMemory:
yield yield
@passive @passive
def write_handler(self, dram_port, wdata_ready_rand_level=0): def write_handler(self, dram_port, wdata_ready_random=0):
address = 0 address = 0
pending = 0 pending = 0
prng = random.Random(42) prng = random.Random(42)
@ -78,7 +72,8 @@ class DRAMMemory:
if pending: if pending:
while (yield dram_port.wdata.valid) == 0: while (yield dram_port.wdata.valid) == 0:
yield yield
yield from rand_wait(wdata_ready_rand_level) while prng.randrange(100) < wdata_ready_random:
yield
yield dram_port.wdata.ready.eq(1) yield dram_port.wdata.ready.eq(1)
yield yield
self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we

68
test/test_axi.py
View file

@ -58,25 +58,27 @@ class Read(Access):
class TestAXI(unittest.TestCase): class TestAXI(unittest.TestCase):
def _test_axi2native(self, def _test_axi2native(self,
naccesses=16, simultaneous_writes_reads=False, naccesses=16, simultaneous_writes_reads=False,
# rand_level: 0: min (no random), 100: max. # random: 0: min (no random), 100: max.
# burst randomness # burst randomness
id_rand_enable = False, id_rand_enable = False,
len_rand_enable = False, len_rand_enable = False,
data_rand_enable = False, data_rand_enable = False,
# flow valid randomness # flow valid randomness
aw_valid_rand_level = 0, aw_valid_random = 0,
w_valid_rand_level = 0, w_valid_random = 0,
ar_valid_rand_level = 0, ar_valid_random = 0,
r_valid_rand_level = 0, r_valid_random = 0,
# flow ready randomness # flow ready randomness
w_ready_rand_level = 0, w_ready_random = 0,
b_ready_rand_level = 0, b_ready_random = 0,
r_ready_rand_level = 0 r_ready_random = 0
): ):
def writes_cmd_generator(axi_port, writes): def writes_cmd_generator(axi_port, writes):
prng = random.Random(42)
for write in writes: for write in writes:
yield from rand_wait(aw_valid_rand_level) while prng.randrange(100) < aw_valid_random:
yield
# send command # send command
yield axi_port.aw.valid.eq(1) yield axi_port.aw.valid.eq(1)
yield axi_port.aw.addr.eq(write.addr<<2) yield axi_port.aw.addr.eq(write.addr<<2)
@ -90,9 +92,11 @@ class TestAXI(unittest.TestCase):
yield axi_port.aw.valid.eq(0) yield axi_port.aw.valid.eq(0)
def writes_data_generator(axi_port, writes): def writes_data_generator(axi_port, writes):
prng = random.Random(42)
for write in writes: for write in writes:
for i, data in enumerate(write.data): for i, data in enumerate(write.data):
yield from rand_wait(w_valid_rand_level) while prng.randrange(100) < w_valid_random:
yield
# send data # send data
yield axi_port.w.valid.eq(1) yield axi_port.w.valid.eq(1)
if (i == (len(write.data) - 1)): if (i == (len(write.data) - 1)):
@ -107,6 +111,7 @@ class TestAXI(unittest.TestCase):
axi_port.reads_enable = True axi_port.reads_enable = True
def writes_response_generator(axi_port, writes): def writes_response_generator(axi_port, writes):
prng = random.Random(42)
self.writes_id_errors = 0 self.writes_id_errors = 0
for write in writes: for write in writes:
# wait response # wait response
@ -114,17 +119,20 @@ class TestAXI(unittest.TestCase):
yield yield
while (yield axi_port.b.valid) == 0: while (yield axi_port.b.valid) == 0:
yield yield
yield from rand_wait(b_ready_rand_level) while prng.randrange(100) < b_ready_random:
yield
yield axi_port.b.ready.eq(1) yield axi_port.b.ready.eq(1)
yield yield
if (yield axi_port.b.id) != write.id: if (yield axi_port.b.id) != write.id:
self.writes_id_errors += 1 self.writes_id_errors += 1
def reads_cmd_generator(axi_port, reads): def reads_cmd_generator(axi_port, reads):
prng = random.Random(42)
while not axi_port.reads_enable: while not axi_port.reads_enable:
yield yield
for read in reads: for read in reads:
yield from rand_wait(ar_valid_rand_level) while prng.randrange(100) < ar_valid_random:
yield
# send command # send command
yield axi_port.ar.valid.eq(1) yield axi_port.ar.valid.eq(1)
yield axi_port.ar.addr.eq(read.addr<<2) yield axi_port.ar.addr.eq(read.addr<<2)
@ -138,6 +146,7 @@ class TestAXI(unittest.TestCase):
yield axi_port.ar.valid.eq(0) yield axi_port.ar.valid.eq(0)
def reads_response_data_generator(axi_port, reads): def reads_response_data_generator(axi_port, reads):
prng = random.Random(42)
self.reads_data_errors = 0 self.reads_data_errors = 0
self.reads_id_errors = 0 self.reads_id_errors = 0
self.reads_last_errors = 0 self.reads_last_errors = 0
@ -150,7 +159,8 @@ class TestAXI(unittest.TestCase):
yield yield
while (yield axi_port.r.valid) == 0: while (yield axi_port.r.valid) == 0:
yield yield
yield from rand_wait(r_ready_rand_level) while prng.randrange(100) < r_ready_random:
yield
yield axi_port.r.ready.eq(1) yield axi_port.r.ready.eq(1)
yield yield
if (yield axi_port.r.data) != data: if (yield axi_port.r.data) != data:
@ -195,8 +205,8 @@ class TestAXI(unittest.TestCase):
writes_response_generator(axi_port, writes), writes_response_generator(axi_port, writes),
reads_cmd_generator(axi_port, reads), reads_cmd_generator(axi_port, reads),
reads_response_data_generator(axi_port, reads), reads_response_data_generator(axi_port, reads),
mem.read_handler(dram_port, rdata_valid_rand_level=r_valid_rand_level), mem.read_handler(dram_port, rdata_valid_random=r_valid_random),
mem.write_handler(dram_port, wdata_ready_rand_level=w_ready_rand_level) mem.write_handler(dram_port, wdata_ready_random=w_ready_random)
] ]
run_simulation(dut, generators) run_simulation(dut, generators)
#mem.show_content() #mem.show_content()
@ -228,25 +238,25 @@ class TestAXI(unittest.TestCase):
data_rand_enable=True) data_rand_enable=True)
def test_axi2native_random_w_ready(self): def test_axi2native_random_w_ready(self):
self._test_axi2native(w_ready_rand_level=90) self._test_axi2native(w_ready_random=90)
def test_axi2native_random_b_ready(self): def test_axi2native_random_b_ready(self):
self._test_axi2native(b_ready_rand_level=90) self._test_axi2native(b_ready_random=90)
def test_axi2native_random_r_ready(self): def test_axi2native_random_r_ready(self):
self._test_axi2native(r_ready_rand_level=90) self._test_axi2native(r_ready_random=90)
def test_axi2native_random_aw_valid(self): def test_axi2native_random_aw_valid(self):
self._test_axi2native(aw_valid_rand_level=90) self._test_axi2native(aw_valid_random=90)
def test_axi2native_random_w_valid(self): def test_axi2native_random_w_valid(self):
self._test_axi2native(w_valid_rand_level=90) self._test_axi2native(w_valid_random=90)
def test_axi2native_random_ar_valid(self): def test_axi2native_random_ar_valid(self):
self._test_axi2native(ar_valid_rand_level=90) self._test_axi2native(ar_valid_random=90)
def test_axi2native_random_r_valid(self): def test_axi2native_random_r_valid(self):
self._test_axi2native(r_valid_rand_level=90) self._test_axi2native(r_valid_random=90)
# now let's stress things a bit... :) # now let's stress things a bit... :)
def test_axi2native_random_all(self): def test_axi2native_random_all(self):
@ -254,11 +264,11 @@ class TestAXI(unittest.TestCase):
simultaneous_writes_reads=True, simultaneous_writes_reads=True,
id_rand_enable=True, id_rand_enable=True,
len_rand_enable=True, len_rand_enable=True,
aw_valid_rand_level=50, aw_valid_random=50,
w_ready_rand_level=50, w_ready_random=50,
b_ready_rand_level=50, b_ready_random=50,
w_valid_rand_level=50, w_valid_random=50,
ar_valid_rand_level=90, ar_valid_random=90,
r_valid_rand_level=90, r_valid_random=90,
r_ready_rand_level=90 r_ready_random=90
) )