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phy/lpddr5/sim: fix incorrect write latency in DRAM simulator
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parent
8c10f1405b
commit
95be0be69d
1 changed files with 12 additions and 8 deletions
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@ -611,8 +611,11 @@ class CommandsSim(Module, AutoCSR):
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self.log.error("WL < 2 is not supported")
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),
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).Else(
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self.data_latency.eq(self.mode_regs.rl - 1),
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If(self.mode_regs.rl < 1,
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# FIXME: Currently we need to subtract 1 cycle here and delay additionally in BurstHalf.
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# We need to check if that's a limitation of PHY not being able to level DRAM only in simulation
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# or if there's a need to increase read_latency by 1 cycle (or increase bitslip cycles).
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self.data_latency.eq(self.mode_regs.rl - 2),
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If(self.mode_regs.rl < 2,
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self.log.error("RL < 2 is not supported")
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),
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),
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@ -759,8 +762,8 @@ class DataSim(Module, AutoCSR):
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self.comb += [
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wr_start.input.eq(cmd.valid & cmd.we & latency_ready),
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rd_start.input.eq(cmd.valid & ~cmd.we & latency_ready),
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delayed_cases(self.burst_p.enable_wr, wr_start, {2: 0, 4: 1}),
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delayed_cases(self.burst_n.enable_wr, wr_start, {2: 1, 4: 2}),
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delayed_cases(self.burst_p.enable_wr, wr_start, {2: 0, 4: 0}),
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delayed_cases(self.burst_n.enable_wr, wr_start, {2: 1, 4: 1}),
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delayed_cases(self.burst_p.enable_rd, rd_start, {2: 0, 4: 0}),
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delayed_cases(self.burst_n.enable_rd, rd_start, {2: 1, 4: 1}),
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cmd.ready.eq(self.burst_p.ready),
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@ -792,6 +795,7 @@ class BurstHalf(Module):
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]
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self.specials += ports
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ports = Array(ports)
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we_all = Signal.like(ports[0].we, reset=2**len(ports[0].we) - 1)
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# Burst control
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burst_length = Signal.like(burst_beat)
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@ -824,13 +828,13 @@ class BurstHalf(Module):
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)
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fsm.act("BURST-WRITE",
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If(cmd_d.masked,
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ports[cmd_d.bank].we.eq(~pads.dmi), # DMI HIGH masks a byte
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ports[cmd_d.bank].we.eq(delayed(self, ~pads.dmi)), # DMI HIGH masks a byte
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).Else(
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ports[cmd_d.bank].we.eq(2**len(ports[cmd_d.bank].we) - 1),
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ports[cmd_d.bank].we.eq(delayed(self, we_all)),
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),
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ports[cmd_d.bank].dat_w.eq(pads.dq),
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ports[cmd_d.bank].dat_w.eq(delayed(self, pads.dq)),
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self.log.debug("WRITE[%d]: bank=%d, row=%d, col=%d, dq=0x%04x dm=0x%02b",
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burst_beat, cmd_d.bank, cmd_d.row, current_col, pads.dq, pads.dmi,
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burst_beat, cmd_d.bank, cmd_d.row, current_col, delayed(self, pads.dq), pads.dmi,
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once=False
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),
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If(self.ready,
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