test: rename read/write generators to handlers

test/common.py

@@ -31,7 +31,7 @@ class DRAMMemory:
             print("0x{:08x}: 0x{:08x}".format(addr, self.mem[addr]))
 
     @passive
-    def read_generator(self, dram_port):
+    def read_handler(self, dram_port):
         address = 0
         pending = 0
         yield dram_port.cmd.ready.eq(0)
@@ -54,7 +54,7 @@ class DRAMMemory:
             yield
 
     @passive
-    def write_generator(self, dram_port):
+    def write_handler(self, dram_port):
         address = 0
         pending = 0
         yield dram_port.cmd.ready.eq(0)

test/test_axi.py

@@ -96,8 +96,8 @@ class TestAXI(unittest.TestCase):
         generators = [
             writes_generator(axi_port, writes),
             reads_generator(axi_port, reads),
-            mem.read_generator(dram_port),
-            mem.write_generator(dram_port)
+            mem.read_handler(dram_port),
+            mem.write_handler(dram_port)
         ]
         run_simulation(dut, generators, vcd_name="axi2native.vcd")
 

test/test_bist.py

@@ -116,7 +116,7 @@ class TestBIST(unittest.TestCase):
         # simulation
         generators = [
             main_generator(dut, mem),
-            mem.write_generator(dut.write_port),
-            mem.read_generator(dut.read_port)
+            mem.write_handler(dut.write_port),
+            mem.read_handler(dut.read_port)
          ]
         run_simulation(dut, generators, vcd_name="bist.vcd")

test/test_downconverter.py

@@ -37,7 +37,7 @@ read_data = []
 
 
 @passive
-def read_generator(read_port):
+def read_handler(read_port):
     yield read_port.rdata.ready.eq(1)
     while True:
         if (yield read_port.rdata.valid):
@@ -83,9 +83,9 @@ class TestDownConverter(unittest.TestCase):
         generators = {
             "sys" : [
                 main_generator(dut.write_user_port, dut.read_user_port),
-                read_generator(dut.read_user_port),
-                dut.memory.write_generator(dut.write_crossbar_port),
-                dut.memory.read_generator(dut.read_crossbar_port)
+                read_handler(dut.read_user_port),
+                dut.memory.write_handler(dut.write_crossbar_port),
+                dut.memory.read_handler(dut.read_crossbar_port)
             ]
         }
         clocks = {"sys": 10}

test/test_upconverter.py

@@ -37,7 +37,7 @@ read_data = []
 
 
 @passive
-def read_generator(read_port):
+def read_handler(read_port):
     yield read_port.rdata.ready.eq(1)
     while True:
         if (yield read_port.rdata.valid):
@@ -86,9 +86,9 @@ class TestUpConverter(unittest.TestCase):
         generators = {
             "sys" :   [
                 main_generator(dut.write_user_port, dut.read_user_port),
-                read_generator(dut.read_user_port),
-                dut.memory.write_generator(dut.write_crossbar_port),
-                dut.memory.read_generator(dut.read_crossbar_port)
+                read_handler(dut.read_user_port),
+                dut.memory.write_handler(dut.write_crossbar_port),
+                dut.memory.read_handler(dut.read_crossbar_port)
             ]
         }
         clocks = {"sys": 10}