test/test_bist: add comments, fix a typo.
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@ -86,6 +86,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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# Generator ------------------------------------------------------------------------------------
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def test_generator(self):
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# Verify Generator is behaving correctly in the incr/random modes.
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def main_generator(dut):
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self.errors = 0
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@ -152,6 +153,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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# _LiteDRAMBISTGenerator -----------------------------------------------------------------------
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def test_bist_generator_8bit(self):
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# Verify BISTGenerator with a 8-bit datapath.
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data = self.bist_test_data["8bit"]
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self.generator_test(data.pop("expected"), data_width=8, config_args=data)
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@ -168,22 +170,27 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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self.assertNotEqual(dut.mem.mem, reference)
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def test_bist_generator_32bit(self):
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# Verify BISTGenerator with a 32-bit datapath.
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data = self.bist_test_data["32bit"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_64bit(self):
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# Verify BISTGenerator with a 64-bit datapath.
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data = self.bist_test_data["64bit"]
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self.generator_test(data.pop("expected"), data_width=64, config_args=data)
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def test_bist_generator_32bit_address_masked(self):
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# Verify BISTGenerator with a 32-bit datapath and masked address.
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data = self.bist_test_data["32bit_masked"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_32bit_long_sequential(self):
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# Verify BISTGenerator with a 32-bit datapath and long sequential pattern.
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data = self.bist_test_data["32bit_long_sequential"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_random_data(self):
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# Verify BISTGenerator with a 32-bit datapath and random pattern.
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data = self.bist_test_data["32bit"]
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data["random_data"] = True
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dut = self.generator_test(data.pop("expected"), data_width=32, config_args=data,
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@ -194,6 +201,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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self.assertNotEqual(mem, list(range(len(mem))), msg="Values are a sequence")
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def test_bist_generator_random_addr(self):
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# Verify BISTGenerator with a 32-bit datapath and random address.
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data = self.bist_test_data["32bit"]
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data["random_addr"] = True
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dut = self.generator_test(data.pop("expected"), data_width=32, config_args=data,
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@ -207,26 +215,32 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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# _LiteDRAMPatternGenerator --------------------------------------------------------------------
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def test_pattern_generator_8bit(self):
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# Verify PatternGenerator with a 8-bit datapath.
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data = self.pattern_test_data["8bit"]
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self.generator_test(data["expected"], data_width=8, pattern=data["pattern"])
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def test_pattern_generator_32bit(self):
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# Verify PatternGenerator with a 32-bit datapath.
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data = self.pattern_test_data["32bit"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_64bit(self):
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# Verify PatternGenerator with a 64-bit datapath.
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data = self.pattern_test_data["64bit"]
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self.generator_test(data["expected"], data_width=64, pattern=data["pattern"])
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def test_pattern_generator_32bit_not_aligned(self):
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# Verify PatternGenerator with a 32-bit datapath and un-aligned addresses.
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data = self.pattern_test_data["32bit_not_aligned"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_32bit_duplicates(self):
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# Verify PatternGenerator with a 32-bit datapath and duplicate addresses.
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data = self.pattern_test_data["32bit_duplicates"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_32bit_sequential(self):
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# Verify PatternGenerator with a 32-bit datapath and sequential pattern.
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data = self.pattern_test_data["32bit_sequential"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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@ -264,39 +278,47 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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return dut, checker
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def test_bist_checker_8bit(self):
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# Verify BISTChecker with a 8-bit datapath.
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data = self.bist_test_data["8bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=8, config_args=data)
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def test_bist_checker_32bit(self):
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# Verify BISTChecker with a 32-bit datapath.
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data = self.bist_test_data["32bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=32, config_args=data)
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def test_bist_checker_64bit(self):
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data = self.bist_test_data["32bit"]
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# Verify BISTChecker with a 64-bit datapath.
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data = self.bist_test_data["64bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=32, config_args=data)
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self.checker_test(memory, data_width=64, config_args=data)
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# _LiteDRAMPatternChecker ----------------------------------------------------------------------
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def test_pattern_checker_8bit(self):
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# Verify PatternChecker with a 8-bit datapath.
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data = self.pattern_test_data["8bit"]
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self.checker_test(memory=data["expected"], data_width=8, pattern=data["pattern"])
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def test_pattern_checker_32bit(self):
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# Verify PatternChecker with a 32-bit datapath.
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data = self.pattern_test_data["32bit"]
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self.checker_test(memory=data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_checker_64bit(self):
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# Verify PatternChecker with a 64-bit datapath.
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data = self.pattern_test_data["64bit"]
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self.checker_test(memory=data["expected"], data_width=64, pattern=data["pattern"])
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def test_pattern_checker_32bit_not_aligned(self):
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# Verify PatternChecker with a 32-bit datapath and un-aligned addresses.
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data = self.pattern_test_data["32bit_not_aligned"]
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self.checker_test(memory=data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_checker_32bit_duplicates(self):
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# Verify PatternChecker with a 32-bit datapath and duplicate addresses.
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data = self.pattern_test_data["32bit_duplicates"]
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num_duplicates = len(data["pattern"]) - len(set(adr for adr, _ in data["pattern"]))
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dut, checker = self.checker_test(
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@ -338,6 +360,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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self.assertEqual(checker.errors, 0)
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def test_bist_base(self):
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# Verify BIST (Generator and Checker) with control from the logic.
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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@ -363,6 +386,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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run_simulation(dut, generators)
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def test_bist_csr(self):
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# Verify BIST (Generator and Checker) with control from CSRs.
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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@ -388,6 +412,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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run_simulation(dut, generators)
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def test_bist_csr_cdc(self):
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# Verify BIST (Generator and Checker) with control from CSRs in a different clock domain.
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class DUT(Module):
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def __init__(self):
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port_kwargs = dict(address_width=32, data_width=32, clock_domain="async")
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