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phy/s7ddrphy: add DDR3-800 timings

This commit is contained in:
Florent Kermarrec 2018-08-21 09:02:57 +02:00
parent 9401b92c71
commit 9a57c4e88c
1 changed files with 5 additions and 2 deletions
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7
litedram/phy/s7ddrphy.py
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@ -1,6 +1,6 @@
# 1:4, 1:2 frequency-ratio DDR2/DDR3 PHY for Xilinx's Series7
# DDR2: 400, 533, 667, 800 and 1066 MT/s
# DDR3: 1066, 1333 and 1600 MT/s
# DDR3: 800, 1066, 1333 and 1600 MT/s
import math
@ -32,8 +32,11 @@ def get_cl_cw(memtype, tck):
else:
raise ValueError
elif memtype == "DDR3":
# ddr3-800
if tck >= 2/800e6:
cl, cwl = 6, 5
# ddr3-1066
if tck >= 2/1066e6:
elif tck >= 2/1066e6:
cl, cwl = 7, 6
# ddr3-1333
elif tck >= 2/1333e6: