phy/s7ddrphy: add DDR3-800 timings
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@ -1,6 +1,6 @@
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# 1:4, 1:2 frequency-ratio DDR2/DDR3 PHY for Xilinx's Series7
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# 1:4, 1:2 frequency-ratio DDR2/DDR3 PHY for Xilinx's Series7
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# DDR2: 400, 533, 667, 800 and 1066 MT/s
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# DDR2: 400, 533, 667, 800 and 1066 MT/s
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# DDR3: 1066, 1333 and 1600 MT/s
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# DDR3: 800, 1066, 1333 and 1600 MT/s
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import math
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import math
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@ -32,8 +32,11 @@ def get_cl_cw(memtype, tck):
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else:
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else:
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raise ValueError
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raise ValueError
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elif memtype == "DDR3":
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elif memtype == "DDR3":
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# ddr3-800
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if tck >= 2/800e6:
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cl, cwl = 6, 5
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# ddr3-1066
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# ddr3-1066
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if tck >= 2/1066e6:
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elif tck >= 2/1066e6:
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cl, cwl = 7, 6
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cl, cwl = 7, 6
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# ddr3-1333
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# ddr3-1333
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elif tck >= 2/1333e6:
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elif tck >= 2/1333e6:
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