ecc: update core/test
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@ -150,8 +150,8 @@ class ECCDecoder(SECDEC, Module):
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class LiteDRAMNativePortECCW(Module):
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class LiteDRAMNativePortECCW(Module):
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def __init__(self, data_width_from, data_width_to):
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def __init__(self, data_width_from, data_width_to):
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self.sink = sink = Endpoint(wdata_description(data_width_from, False))
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self.sink = sink = Endpoint(wdata_description(data_width_from))
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self.source = source = Endpoint(wdata_description(data_width_to, False))
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self.source = source = Endpoint(wdata_description(data_width_to))
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# # #
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# # #
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@ -168,8 +168,8 @@ class LiteDRAMNativePortECCW(Module):
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class LiteDRAMNativePortECCR(Module):
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class LiteDRAMNativePortECCR(Module):
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def __init__(self, data_width_from, data_width_to):
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def __init__(self, data_width_from, data_width_to):
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self.sink = sink = Endpoint(rdata_description(data_width_to, False))
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self.sink = sink = Endpoint(rdata_description(data_width_to))
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self.source = source = Endpoint(rdata_description(data_width_from, False))
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self.source = source = Endpoint(rdata_description(data_width_from))
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self.enable = Signal()
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self.enable = Signal()
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self.sec = Signal(8)
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self.sec = Signal(8)
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self.dec = Signal(8)
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self.dec = Signal(8)
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@ -53,6 +53,7 @@ class TestECC(unittest.TestCase):
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def generator(dut, k, nvalues, nerrors):
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def generator(dut, k, nvalues, nerrors):
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dut.errors = 0
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dut.errors = 0
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prng = random.Random(42)
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prng = random.Random(42)
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yield dut.decoder.enable.eq(1)
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for i in range(nvalues):
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for i in range(nvalues):
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data = prng.randrange(2**k-1)
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data = prng.randrange(2**k-1)
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yield dut.encoder.i.eq(data)
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yield dut.encoder.i.eq(data)
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