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core: replace adr with addr on native interface (closer to AXI and allow some simplifications)

This commit is contained in:
Florent Kermarrec 2018-08-29 17:06:03 +02:00
parent 050670829a
commit 9c729ae7b5
7 changed files with 37 additions and 41 deletions
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16
litedram/common.py
View File

@ -56,14 +56,14 @@ class TimingSettings:
def cmd_layout(address_width):
return [
("valid", 1, DIR_M_TO_S),
("ready", 1, DIR_S_TO_M),
("we", 1, DIR_M_TO_S),
("adr", address_width, DIR_M_TO_S),
("lock", 1, DIR_S_TO_M), # only used internally
("valid", 1, DIR_M_TO_S),
("ready", 1, DIR_S_TO_M),
("we", 1, DIR_M_TO_S),
("addr", address_width, DIR_M_TO_S),
("lock", 1, DIR_S_TO_M), # only used internally
("wdata_ready", 1, DIR_S_TO_M),
("rdata_valid", 1, DIR_S_TO_M)
("wdata_ready", 1, DIR_S_TO_M),
("rdata_valid", 1, DIR_S_TO_M)
]
@ -91,7 +91,7 @@ class LiteDRAMInterface(Record):
def cmd_description(address_width):
return [
("we", 1),
("adr", address_width)
("addr", address_width)
]
def wdata_description(data_width, with_bank):

20
litedram/core/bankmachine.py
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@ -42,14 +42,14 @@ class BankMachine(Module):
auto_precharge = Signal()
# Command buffer
cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
cmd_buffer_layout = [("we", 1), ("addr", len(req.addr))]
cmd_buffer_lookahead = stream.SyncFIFO(
cmd_buffer_layout, settings.cmd_buffer_depth,
buffered=settings.cmd_buffer_buffered)
cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
self.submodules += cmd_buffer_lookahead, cmd_buffer
self.comb += [
req.connect(cmd_buffer_lookahead.sink, keep={"valid", "ready", "we", "adr"}),
req.connect(cmd_buffer_lookahead.sink, keep={"valid", "ready", "we", "addr"}),
cmd_buffer_lookahead.source.connect(cmd_buffer.sink),
cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
req.lock.eq(cmd_buffer_lookahead.source.valid | cmd_buffer.source.valid),
@ -61,7 +61,7 @@ class BankMachine(Module):
has_openrow = Signal()
openrow = Signal(settings.geom.rowbits, reset_less=True)
hit = Signal()
self.comb += hit.eq(openrow == slicer.row(cmd_buffer.source.adr))
self.comb += hit.eq(openrow == slicer.row(cmd_buffer.source.addr))
track_open = Signal()
track_close = Signal()
self.sync += \
@ -69,17 +69,17 @@ class BankMachine(Module):
has_openrow.eq(0)
).Elif(track_open,
has_openrow.eq(1),
openrow.eq(slicer.row(cmd_buffer.source.adr))
openrow.eq(slicer.row(cmd_buffer.source.addr))
)
# Address generation
sel_row_adr = Signal()
sel_row_addr = Signal()
self.comb += [
cmd.ba.eq(n),
If(sel_row_adr,
cmd.a.eq(slicer.row(cmd_buffer.source.adr))
If(sel_row_addr,
cmd.a.eq(slicer.row(cmd_buffer.source.addr))
).Else(
cmd.a.eq((auto_precharge << 10) | slicer.col(cmd_buffer.source.adr))
cmd.a.eq((auto_precharge << 10) | slicer.col(cmd_buffer.source.addr))
)
]
@ -93,7 +93,7 @@ class BankMachine(Module):
if settings.with_auto_precharge:
self.comb += [
If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid,
If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr),
If(slicer.row(cmd_buffer_lookahead.source.addr) != slicer.row(cmd_buffer.source.addr),
auto_precharge.eq((track_close == 0))
)
)
@ -151,7 +151,7 @@ class BankMachine(Module):
track_close.eq(1)
)
fsm.act("ACTIVATE",
sel_row_adr.eq(1),
sel_row_addr.eq(1),
track_open.eq(1),
cmd.valid.eq(ras_allowed),
cmd.is_cmd.eq(1),

10
litedram/frontend/adaptation.py
View File

@ -23,7 +23,7 @@ class LiteDRAMNativePortCDC(Module):
# # #
cmd_fifo = stream.AsyncFIFO(
[("we", 1), ("adr", address_width)], cmd_depth)
[("we", 1), ("addr", address_width)], cmd_depth)
cmd_fifo = ClockDomainsRenamer(
{"write": clock_domain_from,
"read": clock_domain_to})(cmd_fifo)
@ -94,7 +94,7 @@ class LiteDRAMNativePortDownConverter(Module):
fsm.act("CONVERT",
port_to.cmd.valid.eq(1),
port_to.cmd.we.eq(port_from.cmd.we),
port_to.cmd.adr.eq(port_from.cmd.adr*ratio + counter),
port_to.cmd.addr.eq(port_from.cmd.addr*ratio + counter),
If(port_to.cmd.ready,
counter_ce.eq(1),
If(counter == ratio - 1,
@ -164,7 +164,7 @@ class LiteDRAMNativeWritePortUpConverter(Module):
If(port_from.cmd.valid,
counter_ce.eq(1),
NextValue(we, port_from.cmd.we),
NextValue(address, port_from.cmd.adr),
NextValue(address, port_from.cmd.addr),
NextState("RECEIVE")
)
)
@ -180,7 +180,7 @@ class LiteDRAMNativeWritePortUpConverter(Module):
fsm.act("GENERATE",
port_to.cmd.valid.eq(1),
port_to.cmd.we.eq(we),
port_to.cmd.adr.eq(address[log2_int(ratio):]),
port_to.cmd.addr.eq(address[log2_int(ratio):]),
If(port_to.cmd.ready,
NextState("IDLE")
)
@ -235,7 +235,7 @@ class LiteDRAMNativeReadPortUpConverter(Module):
If(port_from.cmd.valid,
If(counter == 0,
port_to.cmd.valid.eq(1),
port_to.cmd.adr.eq(port_from.cmd.adr[log2_int(ratio):]),
port_to.cmd.addr.eq(port_from.cmd.addr[log2_int(ratio):]),
port_from.cmd.ready.eq(port_to.cmd.ready),
counter_ce.eq(port_to.cmd.ready)
).Else(

4
litedram/frontend/axi.py
View File

@ -164,7 +164,7 @@ class LiteDRAMAXI2NativeW(Module):
port.cmd.valid.eq(aw.valid & can_write),
aw.ready.eq(port.cmd.ready & can_write),
port.cmd.we.eq(1),
port.cmd.adr.eq(aw.addr >> ashift)
port.cmd.addr.eq(aw.addr >> ashift)
)
]
@ -234,7 +234,7 @@ class LiteDRAMAXI2NativeR(Module):
port.cmd.valid.eq(ar.valid & can_read),
ar.ready.eq(port.cmd.ready & can_read),
port.cmd.we.eq(0),
port.cmd.adr.eq(ar.addr >> ashift)
port.cmd.addr.eq(ar.addr >> ashift)
)
]

18
litedram/frontend/crossbar.py
View File

@ -54,10 +54,10 @@ class LiteDRAMCrossbar(Module):
# data width convertion
if data_width != self.controller.data_width:
if data_width > self.controller.data_width:
adr_shift = -log2_int(data_width//self.controller.data_width)
addr_shift = -log2_int(data_width//self.controller.data_width)
else:
adr_shift = log2_int(self.controller.data_width//data_width)
new_port = LiteDRAMNativePort(mode, port.address_width + adr_shift, data_width, clock_domain, port.id, with_reordering)
addr_shift = log2_int(self.controller.data_width//data_width)
new_port = LiteDRAMNativePort(mode, port.address_width + addr_shift, data_width, clock_domain, port.id, with_reordering)
self.submodules += ClockDomainsRenamer(clock_domain)(LiteDRAMNativePortConverter(new_port, port, reverse))
port = new_port
@ -113,7 +113,7 @@ class LiteDRAMCrossbar(Module):
# route requests
self.comb += [
bank.adr.eq(Array(m_rca)[arbiter.grant]),
bank.addr.eq(Array(m_rca)[arbiter.grant]),
bank.we.eq(Array(self.masters)[arbiter.grant].cmd.we),
bank.valid.eq(Array(bank_requested)[arbiter.grant])
]
@ -183,15 +183,15 @@ class LiteDRAMCrossbar(Module):
cba = Signal(self.bank_bits)
rca = Signal(self.rca_bits)
cba_upper = cba_shift + bank_bits
self.comb += cba.eq(master.cmd.adr[cba_shift:cba_upper])
self.comb += cba.eq(master.cmd.addr[cba_shift:cba_upper])
if cba_shift < self.rca_bits:
if cba_shift:
self.comb += rca.eq(Cat(master.cmd.adr[:cba_shift],
master.cmd.adr[cba_upper:]))
self.comb += rca.eq(Cat(master.cmd.addr[:cba_shift],
master.cmd.addr[cba_upper:]))
else:
self.comb += rca.eq(master.cmd.adr[cba_upper:])
self.comb += rca.eq(master.cmd.addr[cba_upper:])
else:
self.comb += rca.eq(master.cmd.adr[:cba_shift])
self.comb += rca.eq(master.cmd.addr[:cba_shift])
ba = cba

8
litedram/frontend/dma.py
View File

@ -57,10 +57,8 @@ class LiteDRAMDMAReader(Module):
if is_native:
self.comb += cmd.we.eq(0)
self.comb += cmd.adr.eq(sink.address) # FIXME: use addr for both
if is_axi:
self.comb += cmd.addr.eq(sink.address) # FIXME: use addr for both
self.comb += [
cmd.addr.eq(sink.address),
cmd.valid.eq(sink.valid & request_enable),
sink.ready.eq(cmd.ready & request_enable),
request_issued.eq(cmd.valid & cmd.ready)
@ -133,10 +131,8 @@ class LiteDRAMDMAWriter(Module):
if is_native:
self.comb += cmd.we.eq(1)
self.comb += cmd.adr.eq(sink.address) # FIXME: use addr for both
if is_axi:
self.comb += cmd.addr.eq(sink.address) # FIXME: use addr for both
self.comb += [
cmd.addr.eq(sink.address),
cmd.valid.eq(fifo.sink.ready & sink.valid),
sink.ready.eq(fifo.sink.ready & cmd.ready),
fifo.sink.valid.eq(sink.valid & cmd.ready),

2
litedram/frontend/wishbone.py
View File

@ -43,7 +43,7 @@ class LiteDRAMWishbone2Native(Module):
# Address / Datapath
self.comb += [
port.cmd.adr.eq(wishbone.adr),
port.cmd.addr.eq(wishbone.adr),
port.wdata.we.eq(wishbone.sel),
port.wdata.data.eq(wishbone.dat_w),
wishbone.dat_r.eq(port.rdata.data)