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add W9812G6JB SDRAM module

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Hans Baier 2023-11-09 10:28:39 +07:00
parent 4dec115023
commit 9cffe392ea
1 changed files with 9 additions and 0 deletions
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litedram/modules.py
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@ -553,6 +553,15 @@ class W9825G6KH6(SDRModule):
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 60), tFAW=None, tRAS=42)}
class W9812G6JB(SDRModule):
# geometry
nbanks = 4
nrows = 4096
ncols = 512
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 12))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=20, tRFC=(None, 60), tFAW=None, tRAS=42)}
# DDR ----------------------------------------------------------------------------------------------
class DDRModule(SDRAMModule): memtype = "DDR"