common/LiteDRAMPort: add defaut cd value
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@ -89,7 +89,7 @@ def rdata_description(dw):
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class LiteDRAMPort:
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def __init__(self, aw, dw, cd):
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def __init__(self, aw, dw, cd="sys"):
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self.aw = aw
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self.dw = dw
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self.cd = cd
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