frontend/axi: Add Write Buffer reservation mechanisms to know when we have enough data in the buffer to generate the command.
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@ -43,6 +43,8 @@ class LiteDRAMAXI2NativeW(Module):
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# # #
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# # #
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can_write = Signal()
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ashift = log2_int(port.data_width//8)
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ashift = log2_int(port.data_width//8)
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# Burst to Beat ----------------------------------------------------------------------------
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# Burst to Beat ----------------------------------------------------------------------------
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@ -76,12 +78,31 @@ class LiteDRAMAXI2NativeW(Module):
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resp_buffer.source.connect(axi.b)
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resp_buffer.source.connect(axi.b)
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]
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]
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# Write Buffer reservation ------------------------------------------------------------------
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# - Incremented when data cmd is send
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# - Decremented when data is read
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w_buffer_queue = Signal()
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w_buffer_dequeue = Signal()
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w_buffer_level = Signal(max=buffer_depth + 1)
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self.comb += [
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w_buffer_queue.eq(port.cmd.valid & port.cmd.ready & port.cmd.we),
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w_buffer_dequeue.eq(w_buffer.source.valid & w_buffer.source.ready)
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]
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self.sync += [
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If(w_buffer_queue,
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If(~w_buffer_dequeue, w_buffer_level.eq(w_buffer_level + 1))
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).Elif(w_buffer_dequeue,
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w_buffer_level.eq(w_buffer_level - 1)
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)
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]
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self.comb += can_write.eq(w_buffer.level > w_buffer_level)
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# Command ----------------------------------------------------------------------------------
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# Command ----------------------------------------------------------------------------------
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# Accept and send command to the controller only if:
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# Accept and send command to the controller only if:
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# - Address & Data request are *both* valid.
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# - Address & Data request are *both* valid.
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# - Data buffer is not empty.
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# - Data buffer is not empty.
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self.comb += [
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self.comb += [
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self.cmd_request.eq(aw.valid & w_buffer.source.valid),
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self.cmd_request.eq(aw.valid & can_write),
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If(self.cmd_request & self.cmd_grant,
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If(self.cmd_request & self.cmd_grant,
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port.cmd.valid.eq(1),
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port.cmd.valid.eq(1),
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port.cmd.last.eq(aw.last),
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port.cmd.last.eq(aw.last),
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