litedram/frontend/wishbone: Switch to LiteXModule.
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@ -1,7 +1,7 @@
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2016-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2016-2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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"""Wishbone frontend for LiteDRAM"""
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@ -10,14 +10,17 @@ from math import log2
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from migen import *
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from litex.gen import *
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from litex.soc.interconnect import stream
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from litedram.common import LiteDRAMNativePort
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.adapter import LiteDRAMNativePortConverter
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# LiteDRAMWishbone2Native --------------------------------------------------------------------------
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class LiteDRAMWishbone2Native(Module):
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class LiteDRAMWishbone2Native(LiteXModule):
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def __init__(self, wishbone, port, base_address=0x00000000):
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wishbone_data_width = len(wishbone.dat_w)
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port_data_width = 2**int(log2(len(port.wdata.data))) # Round to lowest power 2
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@ -41,7 +44,7 @@ class LiteDRAMWishbone2Native(Module):
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aborted = Signal()
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offset = base_address >> log2_int(port.data_width//8)
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self.submodules.fsm = fsm = FSM(reset_state="CMD")
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self.fsm = fsm = FSM(reset_state="CMD")
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self.comb += [
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port.cmd.addr.eq(wishbone.adr - offset),
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port.cmd.we.eq(wishbone.we),
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