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Merge pull request #116 from antmicro/jboc/benchmark 

test: add command line arguments for BIST base/length/random
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enjoy-digital 2020-01-28 15:42:27 +01:00 committed by GitHub
parent 72e65e697f 502e6c663c
commit a35a1f7790
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1 changed files with 15 additions and 6 deletions
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21
test/benchmark.py
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@ -26,6 +26,9 @@ class LiteDRAMBenchmarkSoC(SimSoC):
def __init__(self, def __init__(self,
sdram_module = "MT48LC16M16", sdram_module = "MT48LC16M16",
sdram_data_width = 32, sdram_data_width = 32,
bist_base = 0x00000000,
bist_length = 1024,
bist_random = False,
**kwargs): **kwargs):
# SimSoC ----------------------------------------------------------------------------------- # SimSoC -----------------------------------------------------------------------------------
@ -62,18 +65,18 @@ class LiteDRAMBenchmarkSoC(SimSoC):
) )
fsm.act("BIST-GENERATOR", fsm.act("BIST-GENERATOR",
bist_generator.start.eq(1), bist_generator.start.eq(1),
bist_generator.base.eq(0x0000000), # FIXME: make it configurable from command line bist_generator.base.eq(bist_base),
bist_generator.length.eq(1024), # FIXME: make it configurable from command line bist_generator.length.eq(bist_length),
bist_generator.random.eq(0), # FIXME: make it configurable from command line bist_generator.random.eq(bist_random),
If(bist_generator.done, If(bist_generator.done,
NextState("BIST-CHECKER") NextState("BIST-CHECKER")
) )
) )
fsm.act("BIST-CHECKER", fsm.act("BIST-CHECKER",
bist_checker.start.eq(1), bist_checker.start.eq(1),
bist_checker.base.eq(0x0000000), # FIXME: make it configurable from command line bist_checker.base.eq(bist_base),
bist_checker.length.eq(1024), # FIXME: make it configurable from command line bist_checker.length.eq(bist_length),
bist_checker.random.eq(0), # FIXME: make it configurable from command line bist_checker.random.eq(bist_random),
If(bist_checker.done, If(bist_checker.done,
NextState("DISPLAY") NextState("DISPLAY")
) )
@ -114,6 +117,9 @@ def main():
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing") parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing") parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O0", help="Compilation optimization level") parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
args = parser.parse_args() args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args) soc_kwargs = soc_sdram_argdict(args)
@ -125,6 +131,9 @@ def main():
# Configuration -------------------------------------------------------------------------------- # Configuration --------------------------------------------------------------------------------
soc_kwargs["sdram_module"] = args.sdram_module soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width) soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["bist_base"] = int(args.bist_base, 0)
soc_kwargs["bist_length"] = int(args.bist_length, 0)
soc_kwargs["bist_random"] = args.bist_random
# SoC ------------------------------------------------------------------------------------------ # SoC ------------------------------------------------------------------------------------------
soc = LiteDRAMBenchmarkSoC(**soc_kwargs) soc = LiteDRAMBenchmarkSoC(**soc_kwargs)