test/bist_tb: cleanup and add error check
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836a9d4f00
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@ -73,7 +73,7 @@ class LiteDRAMInterface(Record):
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class LiteDRAMPort(Record):
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def __init__(self, aw, dw, cmd_buffer_depth, read_latency, write_latency):
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def __init__(self, aw, dw, cmd_buffer_depth=0, read_latency=0, write_latency=0):
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self.aw = aw
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self.dw = dw
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self.cmd_buffer_depth = cmd_buffer_depth
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@ -8,19 +8,12 @@ from litedram.frontend.bist import LiteDRAMBISTChecker
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class TB(Module):
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def __init__(self):
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self.write_port = LiteDRAMPort(aw=32,
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dw=32,
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cmd_buffer_depth=1,
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read_latency=1,
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write_latency=1)
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self.read_port = LiteDRAMPort(aw=32,
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dw=32,
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cmd_buffer_depth=1,
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read_latency=1,
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write_latency=1)
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self.write_port = LiteDRAMPort(aw=32, dw=32)
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self.read_port = LiteDRAMPort(aw=32, dw=32)
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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class DRAMMemory:
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def __init__(self, width, depth, init=[]):
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self.width = width
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@ -79,7 +72,7 @@ def main_generator(dut):
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yield
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# write
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yield dut.generator.base.storage.eq(16)
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yield dut.generator.length.storage.eq(16)
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yield dut.generator.length.storage.eq(64)
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yield
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yield dut.generator.shoot.re.eq(1)
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yield
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@ -89,7 +82,7 @@ def main_generator(dut):
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yield
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# read
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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yield
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yield dut.checker.shoot.re.eq(1)
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yield
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@ -97,10 +90,13 @@ def main_generator(dut):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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# check
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print("errors {:d}".format((yield dut.checker.error_count.status)))
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yield
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if __name__ == "__main__":
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tb = TB()
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mem = DRAMMemory(32, 1024)
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mem = DRAMMemory(32, 128)
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generators = {
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"sys" : [main_generator(tb),
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mem.write_generator(tb.write_port),
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