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Fix multiple timings ignored

This commit is contained in:
2018-08-14 22:42:02 -04:00
parent 771ccfdc41
commit a4be642d56
1 changed files with 4 additions and 0 deletions
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4
litedram/core/multiplexer.py
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@ -198,10 +198,12 @@ class Multiplexer(Module, AutoCSR):
# tRRD timing (Row to Row delay) # tRRD timing (Row to Row delay)
self.trrdcon = trrdcon = tXXDController(settings.timing.tRRD) self.trrdcon = trrdcon = tXXDController(settings.timing.tRRD)
self.submodules += trrdcon
self.comb += trrdcon.valid.eq(choose_cmd.accept() & choose_cmd.activate()) self.comb += trrdcon.valid.eq(choose_cmd.accept() & choose_cmd.activate())
# tFAW timing (Four Activate Window) # tFAW timing (Four Activate Window)
self.tfawcon = tfawcon = tFAWController(settings.timing.tFAW) self.tfawcon = tfawcon = tFAWController(settings.timing.tFAW)
self.submodules += tfawcon
self.comb += tfawcon.valid.eq(choose_cmd.accept() & choose_cmd.activate()) self.comb += tfawcon.valid.eq(choose_cmd.accept() & choose_cmd.activate())
# RAS control # RAS control
@ -210,6 +212,7 @@ class Multiplexer(Module, AutoCSR):
# tCCD timing (Column to Column delay) # tCCD timing (Column to Column delay)
self.tccdcon = tccdcon = tXXDController(settings.timing.tCCD) self.tccdcon = tccdcon = tXXDController(settings.timing.tCCD)
self.submodules += tccdcon
self.comb += tccdcon.valid.eq(choose_cmd.accept() & (choose_cmd.write() | choose_cmd.read())) self.comb += tccdcon.valid.eq(choose_cmd.accept() & (choose_cmd.write() | choose_cmd.read()))
# CAS control # CAS control
@ -221,6 +224,7 @@ class Multiplexer(Module, AutoCSR):
settings.timing.tWTR + settings.timing.tWTR +
# tCCD must be added since tWTR begins after the transfer is complete # tCCD must be added since tWTR begins after the transfer is complete
settings.timing.tCCD if settings.timing.tCCD is not None else 0) settings.timing.tCCD if settings.timing.tCCD is not None else 0)
self.submodules += twtrcon
self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write()) self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write())
# Read/write turnaround # Read/write turnaround